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SPI implementation panics if read and write buffers in a transfer are not the same length #97

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adamgreig opened this issue Sep 25, 2023 · 1 comment

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@adamgreig
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In embedded-hal SPI transfers, the read and write buffers may be different lengths:

It is allowed for read and write to have different lengths, even zero length. The transfer runs for max(read.len(), write.len()) words. If read is shorter, incoming words after read has been filled will be discarded. If write is shorter, the value of words sent in MOSI after all write has been sent is implementation-defined, typically 0x00, 0xFF, or configurable.

In spidev read_write, it is not:

Note that the tx_buf and rx_buf must be the same length.

However currently we implement transfer by calling read_write directly:

SpiOperation::Transfer(read, write) => SpidevTransfer::read_write(write, read),

leading to panics when the buffer lengths differ. We should adjust the buffers passed to read_write, or split the transfer into a read_write and a write or something, to accommodate.

adamgreig added a commit to adamgreig/linux-embedded-hal that referenced this issue Sep 25, 2023
adamgreig added a commit to adamgreig/linux-embedded-hal that referenced this issue Sep 25, 2023
github-merge-queue bot pushed a commit that referenced this issue Sep 26, 2023
Fix #97: split unbalanced SPI transfers into rw+r or rw+w
@eldruin
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eldruin commented Sep 27, 2023

Fixed in #98. Thank you!

@eldruin eldruin closed this as completed Sep 27, 2023
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