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ManishearthManishearth
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Rollup merge of #101939 - zhaixiaojuan:loongarch64-abi, r=oli-obk
Add loongarch64 abi support
2 parents 01a6f30 + c7961da commit a7cd4f2

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‎compiler/rustc_target/src/abi/call/loongarch.rs

+342
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,342 @@
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use crate::abi::call::{ArgAbi, ArgExtension, CastTarget, FnAbi, PassMode, Reg, RegKind, Uniform};
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use crate::abi::{self, Abi, FieldsShape, HasDataLayout, Size, TyAbiInterface, TyAndLayout};
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use crate::spec::HasTargetSpec;
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#[derive(Copy, Clone)]
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enum RegPassKind {
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Float(Reg),
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Integer(Reg),
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Unknown,
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}
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#[derive(Copy, Clone)]
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enum FloatConv {
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FloatPair(Reg, Reg),
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Float(Reg),
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MixedPair(Reg, Reg),
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}
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#[derive(Copy, Clone)]
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struct CannotUseFpConv;
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fn is_loongarch_aggregate<'a, Ty>(arg: &ArgAbi<'a, Ty>) -> bool {
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match arg.layout.abi {
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Abi::Vector { .. } => true,
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_ => arg.layout.is_aggregate(),
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}
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}
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fn should_use_fp_conv_helper<'a, Ty, C>(
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cx: &C,
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arg_layout: &TyAndLayout<'a, Ty>,
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xlen: u64,
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flen: u64,
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field1_kind: &mut RegPassKind,
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field2_kind: &mut RegPassKind,
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) -> Result<(), CannotUseFpConv>
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where
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Ty: TyAbiInterface<'a, C> + Copy,
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{
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match arg_layout.abi {
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Abi::Scalar(scalar) => match scalar.primitive() {
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abi::Int(..) | abi::Pointer => {
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if arg_layout.size.bits() > xlen {
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return Err(CannotUseFpConv);
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}
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match (*field1_kind, *field2_kind) {
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(RegPassKind::Unknown, _) => {
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*field1_kind = RegPassKind::Integer(Reg {
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kind: RegKind::Integer,
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size: arg_layout.size,
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});
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}
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(RegPassKind::Float(_), RegPassKind::Unknown) => {
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*field2_kind = RegPassKind::Integer(Reg {
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kind: RegKind::Integer,
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size: arg_layout.size,
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});
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}
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_ => return Err(CannotUseFpConv),
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}
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}
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abi::F32 | abi::F64 => {
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if arg_layout.size.bits() > flen {
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return Err(CannotUseFpConv);
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}
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match (*field1_kind, *field2_kind) {
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(RegPassKind::Unknown, _) => {
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*field1_kind =
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RegPassKind::Float(Reg { kind: RegKind::Float, size: arg_layout.size });
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}
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(_, RegPassKind::Unknown) => {
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*field2_kind =
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RegPassKind::Float(Reg { kind: RegKind::Float, size: arg_layout.size });
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}
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_ => return Err(CannotUseFpConv),
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}
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}
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},
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Abi::Vector { .. } | Abi::Uninhabited => return Err(CannotUseFpConv),
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Abi::ScalarPair(..) | Abi::Aggregate { .. } => match arg_layout.fields {
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FieldsShape::Primitive => {
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unreachable!("aggregates can't have `FieldsShape::Primitive`")
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}
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FieldsShape::Union(_) => {
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if !arg_layout.is_zst() {
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return Err(CannotUseFpConv);
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}
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}
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FieldsShape::Array { count, .. } => {
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for _ in 0..count {
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let elem_layout = arg_layout.field(cx, 0);
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should_use_fp_conv_helper(
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cx,
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&elem_layout,
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xlen,
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flen,
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field1_kind,
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field2_kind,
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)?;
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}
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}
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FieldsShape::Arbitrary { .. } => {
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match arg_layout.variants {
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abi::Variants::Multiple { .. } => return Err(CannotUseFpConv),
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abi::Variants::Single { .. } => (),
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}
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for i in arg_layout.fields.index_by_increasing_offset() {
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let field = arg_layout.field(cx, i);
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should_use_fp_conv_helper(cx, &field, xlen, flen, field1_kind, field2_kind)?;
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}
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}
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},
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}
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Ok(())
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}
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fn should_use_fp_conv<'a, Ty, C>(
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cx: &C,
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arg: &TyAndLayout<'a, Ty>,
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xlen: u64,
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flen: u64,
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) -> Option<FloatConv>
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where
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Ty: TyAbiInterface<'a, C> + Copy,
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{
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let mut field1_kind = RegPassKind::Unknown;
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let mut field2_kind = RegPassKind::Unknown;
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if should_use_fp_conv_helper(cx, arg, xlen, flen, &mut field1_kind, &mut field2_kind).is_err() {
129+
return None;
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}
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match (field1_kind, field2_kind) {
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(RegPassKind::Integer(l), RegPassKind::Float(r)) => Some(FloatConv::MixedPair(l, r)),
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(RegPassKind::Float(l), RegPassKind::Integer(r)) => Some(FloatConv::MixedPair(l, r)),
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(RegPassKind::Float(l), RegPassKind::Float(r)) => Some(FloatConv::FloatPair(l, r)),
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(RegPassKind::Float(f), RegPassKind::Unknown) => Some(FloatConv::Float(f)),
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_ => None,
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}
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}
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fn classify_ret<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, xlen: u64, flen: u64) -> bool
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where
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Ty: TyAbiInterface<'a, C> + Copy,
143+
{
144+
if let Some(conv) = should_use_fp_conv(cx, &arg.layout, xlen, flen) {
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match conv {
146+
FloatConv::Float(f) => {
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arg.cast_to(f);
148+
}
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FloatConv::FloatPair(l, r) => {
150+
arg.cast_to(CastTarget::pair(l, r));
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}
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FloatConv::MixedPair(l, r) => {
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arg.cast_to(CastTarget::pair(l, r));
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}
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}
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return false;
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}
158+
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let total = arg.layout.size;
160+
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// "Scalars wider than 2✕XLEN are passed by reference and are replaced in
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// the argument list with the address."
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// "Aggregates larger than 2✕XLEN bits are passed by reference and are
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// replaced in the argument list with the address, as are C++ aggregates
165+
// with nontrivial copy constructors, destructors, or vtables."
166+
if total.bits() > 2 * xlen {
167+
// We rely on the LLVM backend lowering code to lower passing a scalar larger than 2*XLEN.
168+
if is_loongarch_aggregate(arg) {
169+
arg.make_indirect();
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}
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return true;
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}
173+
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let xlen_reg = match xlen {
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32 => Reg::i32(),
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64 => Reg::i64(),
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_ => unreachable!("Unsupported XLEN: {}", xlen),
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};
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if is_loongarch_aggregate(arg) {
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if total.bits() <= xlen {
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arg.cast_to(xlen_reg);
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} else {
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arg.cast_to(Uniform { unit: xlen_reg, total: Size::from_bits(xlen * 2) });
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}
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return false;
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}
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// "When passed in registers, scalars narrower than XLEN bits are widened
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// according to the sign of their type up to 32 bits, then sign-extended to
190+
// XLEN bits."
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extend_integer_width(arg, xlen);
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false
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}
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fn classify_arg<'a, Ty, C>(
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cx: &C,
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arg: &mut ArgAbi<'a, Ty>,
198+
xlen: u64,
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flen: u64,
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is_vararg: bool,
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avail_gprs: &mut u64,
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avail_fprs: &mut u64,
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) where
204+
Ty: TyAbiInterface<'a, C> + Copy,
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{
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if !is_vararg {
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match should_use_fp_conv(cx, &arg.layout, xlen, flen) {
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Some(FloatConv::Float(f)) if *avail_fprs >= 1 => {
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*avail_fprs -= 1;
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arg.cast_to(f);
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return;
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}
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Some(FloatConv::FloatPair(l, r)) if *avail_fprs >= 2 => {
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*avail_fprs -= 2;
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arg.cast_to(CastTarget::pair(l, r));
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return;
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}
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Some(FloatConv::MixedPair(l, r)) if *avail_fprs >= 1 && *avail_gprs >= 1 => {
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*avail_gprs -= 1;
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*avail_fprs -= 1;
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arg.cast_to(CastTarget::pair(l, r));
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return;
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}
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_ => (),
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}
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}
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let total = arg.layout.size;
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let align = arg.layout.align.abi.bits();
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// "Scalars wider than 2✕XLEN are passed by reference and are replaced in
232+
// the argument list with the address."
233+
// "Aggregates larger than 2✕XLEN bits are passed by reference and are
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// replaced in the argument list with the address, as are C++ aggregates
235+
// with nontrivial copy constructors, destructors, or vtables."
236+
if total.bits() > 2 * xlen {
237+
// We rely on the LLVM backend lowering code to lower passing a scalar larger than 2*XLEN.
238+
if is_loongarch_aggregate(arg) {
239+
arg.make_indirect();
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}
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if *avail_gprs >= 1 {
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*avail_gprs -= 1;
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}
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return;
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}
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let double_xlen_reg = match xlen {
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32 => Reg::i64(),
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64 => Reg::i128(),
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_ => unreachable!("Unsupported XLEN: {}", xlen),
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};
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let xlen_reg = match xlen {
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32 => Reg::i32(),
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64 => Reg::i64(),
256+
_ => unreachable!("Unsupported XLEN: {}", xlen),
257+
};
258+
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if total.bits() > xlen {
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let align_regs = align > xlen;
261+
if is_loongarch_aggregate(arg) {
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arg.cast_to(Uniform {
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unit: if align_regs { double_xlen_reg } else { xlen_reg },
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total: Size::from_bits(xlen * 2),
265+
});
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}
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if align_regs && is_vararg {
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*avail_gprs -= *avail_gprs % 2;
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}
270+
if *avail_gprs >= 2 {
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*avail_gprs -= 2;
272+
} else {
273+
*avail_gprs = 0;
274+
}
275+
return;
276+
} else if is_loongarch_aggregate(arg) {
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arg.cast_to(xlen_reg);
278+
if *avail_gprs >= 1 {
279+
*avail_gprs -= 1;
280+
}
281+
return;
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}
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// "When passed in registers, scalars narrower than XLEN bits are widened
285+
// according to the sign of their type up to 32 bits, then sign-extended to
286+
// XLEN bits."
287+
if *avail_gprs >= 1 {
288+
extend_integer_width(arg, xlen);
289+
*avail_gprs -= 1;
290+
}
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}
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fn extend_integer_width<'a, Ty>(arg: &mut ArgAbi<'a, Ty>, xlen: u64) {
294+
if let Abi::Scalar(scalar) = arg.layout.abi {
295+
if let abi::Int(i, _) = scalar.primitive() {
296+
// 32-bit integers are always sign-extended
297+
if i.size().bits() == 32 && xlen > 32 {
298+
if let PassMode::Direct(ref mut attrs) = arg.mode {
299+
attrs.ext(ArgExtension::Sext);
300+
return;
301+
}
302+
}
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}
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}
305+
306+
arg.extend_integer_width_to(xlen);
307+
}
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pub fn compute_abi_info<'a, Ty, C>(cx: &C, fn_abi: &mut FnAbi<'a, Ty>)
310+
where
311+
Ty: TyAbiInterface<'a, C> + Copy,
312+
C: HasDataLayout + HasTargetSpec,
313+
{
314+
let xlen = cx.data_layout().pointer_size.bits();
315+
let flen = match &cx.target_spec().llvm_abiname[..] {
316+
"ilp32f" | "lp64f" => 32,
317+
"ilp32d" | "lp64d" => 64,
318+
_ => 0,
319+
};
320+
321+
let mut avail_gprs = 8;
322+
let mut avail_fprs = 8;
323+
324+
if !fn_abi.ret.is_ignore() && classify_ret(cx, &mut fn_abi.ret, xlen, flen) {
325+
avail_gprs -= 1;
326+
}
327+
328+
for (i, arg) in fn_abi.args.iter_mut().enumerate() {
329+
if arg.is_ignore() {
330+
continue;
331+
}
332+
classify_arg(
333+
cx,
334+
arg,
335+
xlen,
336+
flen,
337+
i >= fn_abi.fixed_count as usize,
338+
&mut avail_gprs,
339+
&mut avail_fprs,
340+
);
341+
}
342+
}

‎compiler/rustc_target/src/abi/call/mod.rs

+2
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ mod arm;
1010
mod avr;
1111
mod bpf;
1212
mod hexagon;
13+
mod loongarch;
1314
mod m68k;
1415
mod mips;
1516
mod mips64;
@@ -696,6 +697,7 @@ impl<'a, Ty> FnAbi<'a, Ty> {
696697
"amdgpu" => amdgpu::compute_abi_info(cx, self),
697698
"arm" => arm::compute_abi_info(cx, self),
698699
"avr" => avr::compute_abi_info(self),
700+
"loongarch64" => loongarch::compute_abi_info(cx, self),
699701
"m68k" => m68k::compute_abi_info(self),
700702
"mips" => mips::compute_abi_info(cx, self),
701703
"mips64" => mips64::compute_abi_info(cx, self),

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