Skip to content

Commit

Permalink
xmsend: Fix FPGA interbyte delay
Browse files Browse the repository at this point in the history
  • Loading branch information
@saursin
saursin committed Mar 10, 2024
1 parent af9803a commit 566fad8
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion scripts/xmsend.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@

InterByteDelay_simt = 0.2 # SIM_WITH_TRACE: simulation with trace
InterByteDelay_sim = 0.005 # NORMAL SIM: 0.001 works, for safety we chose this
InterByteDelay_fpga = 0.001 # FPGA
InterByteDelay_fpga = 0 # FPGA

InterByteDelay = 0

Expand Down

0 comments on commit 566fad8

Please # to comment.