AND16.vhd.bak

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity AND16 is
	port(
		A,B: in std_logic_vector(15 downto 0);
		C  : in std_logic_vector(15 downto 0)
	);
end ADD16

architecture dataflow of AND16 is
	C = A and B;
end dataflow;