JS³Inth

NU EECS392: VLSI Systems Design Projects

Undergraduate Capstone Project

JS³Inth is an FPGA-based Cyclone IV E system on-board synthesizer that implements various synthesizers, volume control and a graphics user interface.

Name		Name	Last commit message	Last commit date
Latest commit History 71 Commits
Deliverables		Deliverables
Wave Math		Wave Math
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
16SampleAdder.vhd.bak		16SampleAdder.vhd.bak
ADD16.vhd.bak		ADD16.vhd.bak
AND16.vhd		AND16.vhd
AND16.vhd.bak		AND16.vhd.bak
FIFO.vhd		FIFO.vhd
FIFO.vhd.bak		FIFO.vhd.bak
FSM_octave.vhd		FSM_octave.vhd
FSM_octave.vhd.bak		FSM_octave.vhd.bak
FSM_synth.vhd		FSM_synth.vhd
FSM_synth.vhd.bak		FSM_synth.vhd.bak
FSM_volume.vhd		FSM_volume.vhd
FSM_volume.vhd.bak		FSM_volume.vhd.bak
JSInth.qpf		JSInth.qpf
JSInth.qsf		JSInth.qsf
JSInth.qws		JSInth.qws
JSInth.vhd		JSInth.vhd
JSInth.vhd.bak		JSInth.vhd.bak
JSInth_nativelink_simulation.rpt		JSInth_nativelink_simulation.rpt
LICENSE		LICENSE
README.md		README.md
SampleAdder16.vhd		SampleAdder16.vhd
SampleAdder16.vhd.bak		SampleAdder16.vhd.bak
SampleContainer.vhd		SampleContainer.vhd
SampleContainer.vhd.bak		SampleContainer.vhd.bak
VGA_top_level.vhd		VGA_top_level.vhd
VGA_top_level.vhd.bak		VGA_top_level.vhd.bak
WM8731_Controller.vhd		WM8731_Controller.vhd
WM8731_Controller.vhd.bak		WM8731_Controller.vhd.bak
audioROM.vhd		audioROM.vhd
audioROM.vhd.bak		audioROM.vhd.bak
colorROM.cmp		colorROM.cmp
colorROM.mif		colorROM.mif
colorROM.qip		colorROM.qip
colorROM.vhd		colorROM.vhd
constants.vhd		constants.vhd
constants.vhd.bak		constants.vhd.bak
de2_i2c_av_config.v		de2_i2c_av_config.v
de2_i2c_av_config.v.bak		de2_i2c_av_config.v.bak
de2_i2c_controller.v		de2_i2c_controller.v
de2_i2c_controller.v.bak		de2_i2c_controller.v.bak
de2_wm8731_audio.vhd.bak		de2_wm8731_audio.vhd.bak
pixelGenerator.vhd		pixelGenerator.vhd
pixelGenerator.vhd.bak		pixelGenerator.vhd.bak
reverb.vhd		reverb.vhd
reverb.vhd.bak		reverb.vhd.bak
reverb.vhd.old		reverb.vhd.old
reverb.vhd.old2		reverb.vhd.old2
reverb.vhd.old3		reverb.vhd.old3
reverb_FIFO.vhd		reverb_FIFO.vhd
reverb_FIFO.vhd.bak		reverb_FIFO.vhd.bak
reverb_adder.vhd		reverb_adder.vhd
reverb_adder.vhd.bak		reverb_adder.vhd.bak
reverb_entity.vhd.old2		reverb_entity.vhd.old2
reverb_tb.bak		reverb_tb.bak
reverb_tb.vhd		reverb_tb.vhd
reverb_tb.vhd.bak		reverb_tb.vhd.bak
streamingContainer.vhd.bak		streamingContainer.vhd.bak
typeDeclarations.vhd		typeDeclarations.vhd
typeDeclarations.vhd.bak		typeDeclarations.vhd.bak
vga_sync.vhd		vga_sync.vhd
vga_sync.vhd.bak		vga_sync.vhd.bak

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JS³Inth

NU EECS392: VLSI Systems Design Projects

Undergraduate Capstone Project

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NU EECS392: VLSI Systems Design Projects

Undergraduate Capstone Project

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