Develop a processor architecture design based on the Y86 ISA using Verilog.
The required specifications in the processor design are as follows:
- A bare minimum processor architecture to implement a sequential design as discussed in Section 4.3 of textbook.
- A full fledged processor architecture implementation with 5 stage pipeline as discussed in Sections 4.4 and 4.5 of textbook, which includes support for eliminating pipeline hazards.
The design approach should be modular, i.e., each stage has to be coded as separate modules and tested independently in order to help the integration without too many issues.