Update examples for new pac

stm32-rs · Dec 16, 2024 · dbe27a0 · dbe27a0
1 parent 6a8f111
commit dbe27a0
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Showing 7 changed files with 14 additions and 10 deletions.
diff --git a/examples/display-dsi-command-teartest-stm32h747i-disco.rs b/examples/display-dsi-command-teartest-stm32h747i-disco.rs
@@ -34,7 +34,7 @@ use cortex_m_rt::{entry, exception};
 use crate::utilities_display::display_target::BufferedDisplay;
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::ltdc;
-use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A;
+use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL;
 use stm32h7xx_hal::{prelude::*, stm32};
 
 use embedded_display_controller::DisplayController;
@@ -186,7 +186,7 @@ fn main() -> ! {
         gpioh.ph5               // SDNWE
     };
 
-    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R);
+    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R);
     // TODO: incorrect for disco!
     let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {};
     let mut sdram = dp.FMC.sdram(

diff --git a/examples/display-dsi-video-stm32h747i-disco.rs b/examples/display-dsi-video-stm32h747i-disco.rs
@@ -29,7 +29,7 @@ use cortex_m_rt::{entry, exception};
 use crate::utilities_display::display_target::BufferedDisplay;
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::ltdc;
-use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A;
+use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL;
 use stm32h7xx_hal::{prelude::*, rtc, stm32};
 
 use embedded_display_controller::DisplayController;
@@ -188,7 +188,7 @@ fn main() -> ! {
         gpioh.ph5               // SDNWE
     };
 
-    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R);
+    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R);
     // TODO: incorrect for disco!
     let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {};
     let mut sdram = dp.FMC.sdram(

diff --git a/examples/display-dsi-video-teartest-stm32h747i-disco.rs b/examples/display-dsi-video-teartest-stm32h747i-disco.rs
@@ -33,7 +33,7 @@ use cortex_m_rt::{entry, exception};
 use crate::utilities_display::display_target::BufferedDisplay;
 use stm32h7xx_hal::gpio::Speed;
 use stm32h7xx_hal::ltdc;
-use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL_A;
+use stm32h7xx_hal::stm32::rcc::d1ccipr::FMCSEL;
 use stm32h7xx_hal::{prelude::*, stm32};
 
 use embedded_display_controller::DisplayController;
@@ -185,7 +185,7 @@ fn main() -> ! {
         gpioh.ph5               // SDNWE
     };
 
-    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL_A::Pll2R);
+    let fmc_ccdr = ccdr.peripheral.FMC.kernel_clk_mux(FMCSEL::Pll2R);
     // TODO: incorrect for disco!
     let sdram_chip = stm32_fmc::devices::is42s32800g_6::Is42s32800g {};
     let mut sdram = dp.FMC.sdram(

diff --git a/examples/ethernet-rtic-stm32h747i-disco.rs b/examples/ethernet-rtic-stm32h747i-disco.rs
@@ -127,7 +127,7 @@ mod app {
         let pwrcfg = pwr.smps().freeze();
 
         // Link the SRAM3 power state to CPU1
-        ctx.device.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
+        ctx.device.RCC.ahb2enr().modify(|_, w| w.sram3en().set_bit());
 
         // Initialise clocks...
         let rcc = ctx.device.RCC.constrain();

diff --git a/examples/ethernet-stm32h747i-disco.rs b/examples/ethernet-stm32h747i-disco.rs
@@ -46,7 +46,7 @@ fn main() -> ! {
 
     // Link the SRAM3 power state to CPU1
     info!("Setup RCC...                  ");
-    dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
+    dp.RCC.ahb2enr().modify(|_, w| w.sram3en().set_bit());
 
     // Initialise clocks...
     let rcc = dp.RCC.constrain();

diff --git a/examples/i2c4_bdma.rs b/examples/i2c4_bdma.rs
@@ -36,8 +36,10 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().expect("Cannot take peripherals");
 
     // Run D3 / SRD domain
-    #[cfg(not(feature = "rm0455"))]
+    #[cfg(not(any(feature = "rm0455", feature = "rm0399")))]
     dp.PWR.cpucr().modify(|_, w| w.run_d3().set_bit());
+    #[cfg(feature = "rm0399")]
+    dp.PWR.cpu1cr().modify(|_, w| w.run_d3().set_bit());
     #[cfg(feature = "rm0455")]
     dp.PWR.cpucr().modify(|_, w| w.run_srd().set_bit());
 

diff --git a/examples/rtic_low_power.rs b/examples/rtic_low_power.rs
@@ -56,8 +56,10 @@ mod app {
         let mut syscfg = ctx.device.SYSCFG;
 
         // Run D3 / SRD domain
-        #[cfg(not(feature = "rm0455"))]
+        #[cfg(not(any(feature = "rm0455", feature = "rm0399")))]
         ctx.device.PWR.cpucr().modify(|_, w| w.run_d3().set_bit());
+        #[cfg(feature = "rm0399")]
+        ctx.device.PWR.cpu1cr().modify(|_, w| w.run_d3().set_bit());
         #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts
         ctx.device.PWR.cpucr().modify(|_, w| w.run_srd().set_bit());