variant(g4): Fix clock config of WeAct STM32G474CoreBoard #2619
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* Override HSE value to 8 MHz not 24 * Keep PLL input above 2.66 MHz spec * Set VCO to a multiple of USB48 and feed that from PLL, sysclk becomes 144
* Enable CRS and switch USB to HSI48, decoupling it from PLL * Increase VCO multiplier to reach 170 MHz max spec
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Summary
This PR fixes the following bugs:
Not touching generic_clock.cpp, that looks fine (HSI16 div4 into 150 MHz and CRS HSI48). I would like to rename its
RCC_CRSInitTypeDef pInittoRCC_CRSInitStructlike in this patch but it's up to naming convention, not relevant to compiled code.LPUART1 clocksource defaults to Pclk1, I think, no need to switch it to Sysclk or HSI or LSE (because LSE XTAL is behind DNI solderbridges).
Validation
Code formatting
CI/astyle/astyle.pylocally.Closing issues
Follow-up to #2615