Merge pull request #369 from stnolting/dependabot/submodules/neorv32-…

…fc0034f [Dependabot]: Bump neorv32 from `3d986cb` to `fc0034f`
stnolting · Dec 23, 2024 · 9ae36d2 · 9ae36d2
2 parents e1ae3d8 + 702431b
commit 9ae36d2
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Showing 2 changed files with 27 additions and 27 deletions.
diff --git a/neorv32 b/neorv32
diff --git a/sim/neorv32_riscof_tb.vhd b/sim/neorv32_riscof_tb.vhd
@@ -139,38 +139,38 @@ begin
   neorv32_top_inst: neorv32_top
   generic map (
     -- Processor Clocking --
-    CLOCK_FREQUENCY  => 100_000_000,
+    CLOCK_FREQUENCY   => 100_000_000,
     -- Boot Configuration --
-    BOOT_MODE_SELECT => 1, -- boot from BOOT_ADDR_CUSTOM
-    BOOT_ADDR_CUSTOM => x"00000000",
+    BOOT_MODE_SELECT  => 1, -- boot from BOOT_ADDR_CUSTOM
+    BOOT_ADDR_CUSTOM  => x"00000000",
     -- RISC-V CPU Extensions --
-    RISCV_ISA_C      => true,
-    RISCV_ISA_M      => true,
-    RISCV_ISA_U      => true,
-    RISCV_ISA_Zba    => true,
-    RISCV_ISA_Zbb    => true,
-    RISCV_ISA_Zbkb   => true,
-    RISCV_ISA_Zbkc   => true,
-    RISCV_ISA_Zbkx   => true,
-    RISCV_ISA_Zbs    => true,
-    RISCV_ISA_Zicntr => true,
-    RISCV_ISA_Zicond => true,
-    RISCV_ISA_Zknd   => true,
-    RISCV_ISA_Zkne   => true,
-    RISCV_ISA_Zknh   => true,
-    RISCV_ISA_Zksed  => true,
-    RISCV_ISA_Zksh   => true,
+    RISCV_ISA_C       => true,
+    RISCV_ISA_M       => true,
+    RISCV_ISA_U       => true,
+    RISCV_ISA_Zba     => true,
+    RISCV_ISA_Zbb     => true,
+    RISCV_ISA_Zbkb    => true,
+    RISCV_ISA_Zbkc    => true,
+    RISCV_ISA_Zbkx    => true,
+    RISCV_ISA_Zbs     => true,
+    RISCV_ISA_Zicntr  => true,
+    RISCV_ISA_Zicond  => true,
+    RISCV_ISA_Zknd    => true,
+    RISCV_ISA_Zkne    => true,
+    RISCV_ISA_Zknh    => true,
+    RISCV_ISA_Zksed   => true,
+    RISCV_ISA_Zksh    => true,
     -- Tuning Options --
-    FAST_MUL_EN      => true,
-    FAST_SHIFT_EN    => true,
+    CPU_FAST_MUL_EN   => true,
+    CPU_FAST_SHIFT_EN => true,
     -- Internal Instruction memory --
-    MEM_INT_IMEM_EN  => false,
+    MEM_INT_IMEM_EN   => false,
     -- Internal Data memory --
-    MEM_INT_DMEM_EN  => false,
+    MEM_INT_DMEM_EN   => false,
     -- External bus interface --
-    XBUS_EN          => true,
-    XBUS_TIMEOUT     => 7,
-    XBUS_REGSTAGE_EN => false
+    XBUS_EN           => true,
+    XBUS_TIMEOUT      => 7,
+    XBUS_REGSTAGE_EN  => false
   )
   port map (
     -- Global control --
+4 −0		CHANGELOG.md
+93 −51		docs/datasheet/cpu.adoc
+5 −4		docs/datasheet/cpu_csr.adoc
+1 −6		docs/datasheet/overview.adoc
+10 −24		docs/datasheet/soc.adoc
+1 −1		docs/datasheet/soc_sysinfo.adoc
+0 −2		docs/userguide/content.adoc
+22 −26		docs/userguide/eclipse_ide.adoc
+74 −81		docs/userguide/simulating_the_processor.adoc
+0 −12		docs/userguide/vhdl_development_environment.adoc
+40 −37		rtl/core/neorv32_application_image.vhd
+5 −5		rtl/core/neorv32_bootloader_image.vhd
+126 −28		rtl/core/neorv32_bus.vhd
+2 −2		rtl/core/neorv32_cache.vhd
+98 −78		rtl/core/neorv32_cpu.vhd
+203 −245		rtl/core/neorv32_cpu_control.vhd
+4 −2		rtl/core/neorv32_cpu_cp_crypto.vhd
+4 −8		rtl/core/neorv32_cpu_lsu.vhd
+136 −151		rtl/core/neorv32_cpu_pmp.vhd
+25 −5		rtl/core/neorv32_package.vhd
+1 −2		rtl/core/neorv32_sysinfo.vhd
+13 −32		rtl/core/neorv32_top.vhd
+19 −19		rtl/core/neorv32_xirq.vhd
+1 −0		rtl/file_list_cpu.f
+3 −3		rtl/system_integration/neorv32_vivado_ip.tcl
+7 −7		rtl/system_integration/neorv32_vivado_ip.vhd
+0 −46		sim/ghdl.run.sh
+39 −4		sim/ghdl.sh
+51 −50		sim/neorv32_tb.vhd
+9 −8		sw/common/common.mk
+60 −54		sw/image_gen/image_gen.c
+2 −1		sw/lib/include/neorv32_cpu_csr.h
+1 −1		sw/lib/include/neorv32_sysinfo.h
+1 −1		sw/lib/source/neorv32_rte.c
+2 −2		sw/lib/source/neorv32_uart.c
+0 −1		sw/svd/neorv32.svd