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Fix Vivado TCL #212

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merged 2 commits into from
Jan 6, 2025
Merged

Fix Vivado TCL #212

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87bcdce
Fix Arty TCL
Unike267 Jan 5, 2025
14ee915
Fix Nexys TCL
Unike267 Jan 5, 2025
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2 changes: 1 addition & 1 deletion vivado/arty-a7-test-setup/create_project.tcl
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Expand Up @@ -38,7 +38,7 @@ set fileset_design ./../../neorv32/rtl/test_setups/neorv32_test_setup_bootloader
set fileset_constraints [glob ./*.xdc]

## Simulation-only sources
set fileset_sim [list ./../../neorv32/sim/simple/neorv32_tb.simple.vhd ./../../neorv32/sim/simple/uart_rx.simple.vhd]
set fileset_sim [list ./../../neorv32/sim/neorv32_tb.vhd ./../../neorv32/sim/sim_uart_rx.vhd]

# Add source files

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2 changes: 1 addition & 1 deletion vivado/nexys-a7-test-setup/create_project.tcl
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Expand Up @@ -34,7 +34,7 @@ set_property library neorv32 [get_files [glob ./../../neorv32/rtl/core/*.vhd]]
add_files [glob ./../../neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd]

# add source files: simulation-only
add_files -fileset sim_1 [list ./../../neorv32/sim/simple/neorv32_tb.simple.vhd ./../../neorv32/sim/simple/uart_rx.simple.vhd]
add_files -fileset sim_1 [list ./../../neorv32/sim/neorv32_tb.vhd ./../../neorv32/sim/sim_uart_rx.vhd]

# add source files: constraints
add_files -fileset constrs_1 [glob ./*.xdc]
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