[cpu] rename tuning option generics

stnolting · Dec 22, 2024 · 311f356 · 311f356
1 parent 70c76d4
commit 311f356
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diff --git a/docs/datasheet/cpu.adoc b/docs/datasheet/cpu.adoc
@@ -259,7 +259,7 @@ Software can check for configured tuning options via specific flags in the <<_mx
 
 {empty} +
 [discrete]
-===== **`CLOCK_GATING_EN`**
+===== **`CPU_CLOCK_GATING_EN`**
 
 [cols="<1,<8"]
 [frame="topbot",grid="none"]
@@ -274,7 +274,7 @@ Software can check for configured tuning options via specific flags in the <<_mx
 
 {empty} +
 [discrete]
-===== **`FAST_MUL_EN`**
+===== **`CPU_FAST_MUL_EN`**
 
 [cols="<1,<8"]
 [frame="topbot",grid="none"]
@@ -293,7 +293,7 @@ time-independent of the provided operands.
 
 {empty} +
 [discrete]
-===== **`FAST_SHIFT_EN`**
+===== **`CPU_FAST_SHIFT_EN`**
 
 [cols="<1,<8"]
 [frame="topbot",grid="none"]
@@ -314,7 +314,7 @@ approach requires only a few hardware resources and does not impact the critical
 
 {empty} +
 [discrete]
-===== **`REGFILE_HW_RST`**
+===== **`CPU_REGFILE_HW_RST`**
 
 [cols="<1,<8"]
 [frame="topbot",grid="none"]
@@ -360,7 +360,7 @@ The single clock domain of the CPU core can be split into an always-on clock dom
 The switchable clock domain can be deactivated to further reduce reduce dynamic power consumption. CPU-external modules
 like timers, interfaces and memories are not affected by the clock gating.
 
-The splitting into two clock domain is enabled by the `CLOCK_GATING_EN` generic (<<_processor_top_entity_generics>> /
+The splitting into two clock domain is enabled by the `CPU_CLOCK_GATING_EN` generic (<<_processor_top_entity_generics>> /
 <<_cpu_tuning_options>>). When enabled, a generic clock switching gate is added to decouple the switchable clock from
 the always-on clock domain. Whenever the CPU enters <<_sleep_mode>> the switchable clock domain is shut down.
 
@@ -583,7 +583,7 @@ The "compressed" ISA extension provides 16-bit encodings of commonly used instru
 |=======================
 | Class | Instructions | Execution cycles
 | ALU           | `c.addi4spn` `c.nop` `c.add[i]` `c.li` `c.addi16sp` `c.lui` `c.and[i]` `c.sub` `c.xor` `c.or` `c.mv` | 2
-| ALU           | `c.srli` `c.srai` `c.slli`                                                                           | 3 + 1..32; FAST_SHIFT: 4
+| ALU           | `c.srli` `c.srai` `c.slli`                                                                           | 3 + 1..32; `CPU_FAST_SHIFT_EN`: 4
 | Branches      | `c.beqz` `c.bnez`                                                                                    | taken: 6; not taken: 3
 | Jumps / calls | `c.jal[r]` `c.j` `c.jr`                                                                              | 6
 | Memory access | `c.lw` `c.sw` `c.lwsp` `c.swsp`                                                                      | 4
@@ -612,7 +612,7 @@ The `I` ISA extensions is the base RISC-V integer ISA that is always enabled.
 | Class | Instructions | Execution cycles
 | ALU           | `add[i]` `slt[i]` `slt[i]u` `xor[i]` `or[i]` `and[i]` `sub` `lui` `auipc` | 2
 | No-operation  | "`nop`"                                                                   | 2
-| ALU shifts    | `sll[i]` `srl[i]` `sra[i]`                                                | 3 + 1..32; FAST_SHIFT: 4
+| ALU shifts    | `sll[i]` `srl[i]` `sra[i]`                                                | 3 + 1..32; `CPU_FAST_SHIFT_EN`: 4
 | Branches      | `beq` `bne` `blt` `bge` `bltu` `bgeu`                                     | taken: 6; not taken: 3
 | Jump/call     | `jal[r]`                                                                  | 6
 | Load/store    | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw`                                 | 5
@@ -651,7 +651,7 @@ This ISA extension is implemented as multi-cycle ALU co-process (`rtl/core/neorv
 [options="header", grid="rows"]
 |=======================
 | Class | Instructions | Execution cycles
-| Multiplication | `mul` `mulh` `mulhsu` `mulhu` | 36; FAST_MUL: 4
+| Multiplication | `mul` `mulh` `mulhsu` `mulhu` | 36; `CPU_FAST_MUL_EN`: 4
 | Division       | `div` `divu` `rem` `remu`     | 36
 |=======================
 
@@ -873,11 +873,11 @@ generic. This ISA extension is implemented as multi-cycle ALU co-processor (`rtl
 |=======================
 | Class | Instructions | Execution cycles
 | Logic with negate            | `andn` `orn` `xnor`      | 4
-| Count leading/trailing zeros | `clz` `ctz`              | 6 + 1..32; FAST_SHIFT: 4
-| Count population             | `cpop`                   | 6 + 32; FAST_SHIFT: 4
+| Count leading/trailing zeros | `clz` `ctz`              | 6 + 1..32; `CPU_FAST_SHIFT_EN`: 4
+| Count population             | `cpop`                   | 6 + 32; `CPU_FAST_SHIFT_EN`: 4
 | Integer maximum/minimum      | `min[u]` `max[u]`        | 4
 | Sign/zero extension          | `sext.b` `sext.h` `zext` | 4
-| Bitwise rotation             | `rol` `ror[i]`           | 6 + _shift_amount_; FAST_SHIFT: 4
+| Bitwise rotation             | `rol` `ror[i]`           | 6 + _shift_amount_; `CPU_FAST_SHIFT_EN`: 4
 | OR-combine                   | `orc.b`                  | 4
 | Byte-reverse                 | `rev8`                   | 4
 |=======================
@@ -1078,13 +1078,13 @@ core does implement must adhere to the requirements of `Zkt`.
 |=======================
 | Parent extension | Instructions | Data independent execution time?
 .2+<| `RVI` <| `lui` `auipc` `add[i]` `slt[i][u]` `xor[i]` `or[i]` `and[i]` `sub` <| yes
-            <| `sll[i]` `srl[i]` `sra[i]` <| yes if `FAST_SHIFT_EN` enabled
+            <| `sll[i]` `srl[i]` `sra[i]` <| yes if `CPU_FAST_SHIFT_EN` enabled
 | `RVM` | `mul[h]` `mulh[s]u` | yes
 .2+<| `RVC` <| `c.nop` `c.addi` `c.lui` `c.andi` `c.sub` `c.xor` `c.and` `c.mv` `c.add` <| yes
-            <| `c.srli` `c.srai` `c.slli` <| yes if `FAST_SHIFT_EN` enabled
+            <| `c.srli` `c.srai` `c.slli` <| yes if `CPU_FAST_SHIFT_EN` enabled
 | `RVK` | `aes32ds[m]i` `aes32es[m]i` `sha256sig*` `sha512sig*` `sha512sum*` `sm3p0` `sm3p1` `sm4ed` `sm4ks` | yes
 .2+<| `RVB` <| `xperm4` `xperm8` `andn` `orn` `xnor` `pack[h]` `brev8` `rev8` <| yes
-            <| `ror[i]` `rol` <| yes if `FAST_SHIFT_EN` enabled
+            <| `ror[i]` `rol` <| yes if `CPU_FAST_SHIFT_EN` enabled
 |=======================
 
 

diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd
@@ -54,10 +54,10 @@ entity neorv32_cpu is
     RISCV_ISA_Sdtrig    : boolean; -- implement trigger module extension
     RISCV_ISA_Smpmp     : boolean; -- implement physical memory protection
     -- Tuning Options --
-    CLOCK_GATING_EN     : boolean; -- enable clock gating when in sleep mode
-    FAST_MUL_EN         : boolean; -- use DSPs for M extension's multiplier
-    FAST_SHIFT_EN       : boolean; -- use barrel shifter for shift operations
-    REGFILE_HW_RST      : boolean; -- implement full hardware reset for register file
+    CPU_CLOCK_GATING_EN : boolean; -- enable clock gating when in sleep mode
+    CPU_FAST_MUL_EN     : boolean; -- use DSPs for M extension's multiplier
+    CPU_FAST_SHIFT_EN   : boolean; -- use barrel shifter for shift operations
+    CPU_REGFILE_HW_RST  : boolean; -- implement full hardware reset for register file
     -- Physical Memory Protection (PMP) --
     PMP_NUM_REGIONS     : natural range 0 to 16; -- number of regions (0..16)
     PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
@@ -93,7 +93,7 @@ architecture neorv32_cpu_rtl of neorv32_cpu is
   -- auto-configuration --
   constant rf_rs3_en_c : boolean := RISCV_ISA_Zxcfu or RISCV_ISA_Zfinx; -- 3rd register file read port
   constant riscv_b_c   : boolean := RISCV_ISA_Zba and RISCV_ISA_Zbb and RISCV_ISA_Zbs; -- B: bit manipulation
-  constant riscv_zkt_c : boolean := FAST_SHIFT_EN; -- Zkt: data-independent execution time for cryptographic operations
+  constant riscv_zkt_c : boolean := CPU_FAST_SHIFT_EN; -- Zkt: data-independent execution time for cryptographic operations
   constant riscv_zkn_c : boolean := RISCV_ISA_Zbkb and RISCV_ISA_Zbkc and RISCV_ISA_Zbkx and
                                     RISCV_ISA_Zkne and RISCV_ISA_Zknd and RISCV_ISA_Zknh; -- Zkn: NIST suite
   constant riscv_zks_c : boolean := RISCV_ISA_Zbkb and RISCV_ISA_Zbkc and RISCV_ISA_Zbkx and
@@ -170,9 +170,10 @@ begin
 
   -- CPU tuning options --
   assert false report "[NEORV32] CPU tuning options: " &
-    cond_sel_string_f(FAST_MUL_EN,    "fast_mul ",   "") &
-    cond_sel_string_f(FAST_SHIFT_EN,  "fast_shift ", "") &
-    cond_sel_string_f(REGFILE_HW_RST, "rf_hw_rst ",  "")
+    cond_sel_string_f(CPU_CLOCK_GATING_EN, "clock_gating ", "") &
+    cond_sel_string_f(CPU_FAST_MUL_EN,     "fast_mul ",     "") &
+    cond_sel_string_f(CPU_FAST_SHIFT_EN,   "fast_shift ",   "") &
+    cond_sel_string_f(CPU_REGFILE_HW_RST,  "rf_hw_rst ",    "")
     severity note;
 
   -- simulation notifier --
@@ -182,7 +183,7 @@ begin
   -- Clock Gating ---------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   neorv32_cpu_clockgate_enabled:
-  if CLOCK_GATING_EN generate
+  if CPU_CLOCK_GATING_EN generate
     neorv32_cpu_clockgate_inst: entity neorv32.neorv32_clockgate
     port map (
       clk_i  => clk_i,
@@ -193,7 +194,7 @@ begin
   end generate;
 
   neorv32_cpu_clockgate_disabled:
-  if not CLOCK_GATING_EN generate
+  if not CPU_CLOCK_GATING_EN generate
     clk_gated <= clk_i;
   end generate;
 
@@ -203,49 +204,49 @@ begin
   neorv32_cpu_control_inst: entity neorv32.neorv32_cpu_control
   generic map (
     -- General --
-    HART_ID          => HART_ID,          -- hardware thread ID
-    VENDOR_ID        => VENDOR_ID,        -- vendor's JEDEC ID
-    BOOT_ADDR        => BOOT_ADDR,        -- cpu boot address
-    DEBUG_PARK_ADDR  => DEBUG_PARK_ADDR,  -- cpu debug mode parking loop entry address
-    DEBUG_EXC_ADDR   => DEBUG_EXC_ADDR,   -- cpu debug mode exception entry address
+    HART_ID             => HART_ID,          -- hardware thread ID
+    VENDOR_ID           => VENDOR_ID,        -- vendor's JEDEC ID
+    BOOT_ADDR           => BOOT_ADDR,        -- cpu boot address
+    DEBUG_PARK_ADDR     => DEBUG_PARK_ADDR,  -- cpu debug mode parking loop entry address
+    DEBUG_EXC_ADDR      => DEBUG_EXC_ADDR,   -- cpu debug mode exception entry address
     -- RISC-V ISA Extensions --
-    RISCV_ISA_B      => riscv_b_c,        -- implement bit-manipulation extension
-    RISCV_ISA_C      => RISCV_ISA_C,      -- implement compressed extension
-    RISCV_ISA_E      => RISCV_ISA_E,      -- implement embedded RF extension
-    RISCV_ISA_M      => RISCV_ISA_M,      -- implement mul/div extension
-    RISCV_ISA_U      => RISCV_ISA_U,      -- implement user mode extension
-    RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, -- implement atomic reservation-set extension
-    RISCV_ISA_Zba    => RISCV_ISA_Zba,    -- implement shifted-add bit-manipulation extension
-    RISCV_ISA_Zbb    => RISCV_ISA_Zbb,    -- implement basic bit-manipulation extension
-    RISCV_ISA_Zbkb   => RISCV_ISA_Zbkb,   -- implement bit-manipulation instructions for cryptography
-    RISCV_ISA_Zbkc   => RISCV_ISA_Zbkc,   -- implement carry-less multiplication instructions
-    RISCV_ISA_Zbkx   => RISCV_ISA_Zbkx,   -- implement cryptography crossbar permutation extension
-    RISCV_ISA_Zbs    => RISCV_ISA_Zbs,    -- implement single-bit bit-manipulation extension
-    RISCV_ISA_Zfinx  => RISCV_ISA_Zfinx,  -- implement 32-bit floating-point extension
-    RISCV_ISA_Zicntr => RISCV_ISA_Zicntr, -- implement base counters
-    RISCV_ISA_Zicond => RISCV_ISA_Zicond, -- implement integer conditional operations
-    RISCV_ISA_Zihpm  => RISCV_ISA_Zihpm,  -- implement hardware performance monitors
-    RISCV_ISA_Zkn    => riscv_zkn_c,      -- NIST algorithm suite available
-    RISCV_ISA_Zknd   => RISCV_ISA_Zknd,   -- implement cryptography NIST AES decryption extension
-    RISCV_ISA_Zkne   => RISCV_ISA_Zkne,   -- implement cryptography NIST AES encryption extension
-    RISCV_ISA_Zknh   => RISCV_ISA_Zknh,   -- implement cryptography NIST hash extension
-    RISCV_ISA_Zks    => riscv_zks_c,      -- ShangMi algorithm suite available
-    RISCV_ISA_Zksed  => RISCV_ISA_Zksed,  -- implement ShangMi block cypher extension
-    RISCV_ISA_Zksh   => RISCV_ISA_Zksh,   -- implement ShangMi hash extension
-    RISCV_ISA_Zkt    => riscv_zkt_c,      -- data-independent execution time available (for cryptographic operations)
-    RISCV_ISA_Zmmul  => RISCV_ISA_Zmmul,  -- implement multiply-only M sub-extension
-    RISCV_ISA_Zxcfu  => RISCV_ISA_Zxcfu,  -- implement custom (instr.) functions unit
-    RISCV_ISA_Sdext  => RISCV_ISA_Sdext,  -- implement external debug mode extension
-    RISCV_ISA_Sdtrig => RISCV_ISA_Sdtrig, -- implement trigger module extension
-    RISCV_ISA_Smpmp  => RISCV_ISA_Smpmp,  -- implement physical memory protection
+    RISCV_ISA_B         => riscv_b_c,        -- implement bit-manipulation extension
+    RISCV_ISA_C         => RISCV_ISA_C,      -- implement compressed extension
+    RISCV_ISA_E         => RISCV_ISA_E,      -- implement embedded RF extension
+    RISCV_ISA_M         => RISCV_ISA_M,      -- implement mul/div extension
+    RISCV_ISA_U         => RISCV_ISA_U,      -- implement user mode extension
+    RISCV_ISA_Zalrsc    => RISCV_ISA_Zalrsc, -- implement atomic reservation-set extension
+    RISCV_ISA_Zba       => RISCV_ISA_Zba,    -- implement shifted-add bit-manipulation extension
+    RISCV_ISA_Zbb       => RISCV_ISA_Zbb,    -- implement basic bit-manipulation extension
+    RISCV_ISA_Zbkb      => RISCV_ISA_Zbkb,   -- implement bit-manipulation instructions for cryptography
+    RISCV_ISA_Zbkc      => RISCV_ISA_Zbkc,   -- implement carry-less multiplication instructions
+    RISCV_ISA_Zbkx      => RISCV_ISA_Zbkx,   -- implement cryptography crossbar permutation extension
+    RISCV_ISA_Zbs       => RISCV_ISA_Zbs,    -- implement single-bit bit-manipulation extension
+    RISCV_ISA_Zfinx     => RISCV_ISA_Zfinx,  -- implement 32-bit floating-point extension
+    RISCV_ISA_Zicntr    => RISCV_ISA_Zicntr, -- implement base counters
+    RISCV_ISA_Zicond    => RISCV_ISA_Zicond, -- implement integer conditional operations
+    RISCV_ISA_Zihpm     => RISCV_ISA_Zihpm,  -- implement hardware performance monitors
+    RISCV_ISA_Zkn       => riscv_zkn_c,      -- NIST algorithm suite available
+    RISCV_ISA_Zknd      => RISCV_ISA_Zknd,   -- implement cryptography NIST AES decryption extension
+    RISCV_ISA_Zkne      => RISCV_ISA_Zkne,   -- implement cryptography NIST AES encryption extension
+    RISCV_ISA_Zknh      => RISCV_ISA_Zknh,   -- implement cryptography NIST hash extension
+    RISCV_ISA_Zks       => riscv_zks_c,      -- ShangMi algorithm suite available
+    RISCV_ISA_Zksed     => RISCV_ISA_Zksed,  -- implement ShangMi block cypher extension
+    RISCV_ISA_Zksh      => RISCV_ISA_Zksh,   -- implement ShangMi hash extension
+    RISCV_ISA_Zkt       => riscv_zkt_c,      -- data-independent execution time available (for cryptographic operations)
+    RISCV_ISA_Zmmul     => RISCV_ISA_Zmmul,  -- implement multiply-only M sub-extension
+    RISCV_ISA_Zxcfu     => RISCV_ISA_Zxcfu,  -- implement custom (instr.) functions unit
+    RISCV_ISA_Sdext     => RISCV_ISA_Sdext,  -- implement external debug mode extension
+    RISCV_ISA_Sdtrig    => RISCV_ISA_Sdtrig, -- implement trigger module extension
+    RISCV_ISA_Smpmp     => RISCV_ISA_Smpmp,  -- implement physical memory protection
     -- Tuning Options --
-    CLOCK_GATING_EN  => CLOCK_GATING_EN,  -- enable clock gating when in sleep mode
-    FAST_MUL_EN      => FAST_MUL_EN,      -- use DSPs for M extension's multiplier
-    FAST_SHIFT_EN    => FAST_SHIFT_EN,    -- use barrel shifter for shift operations
-    REGFILE_HW_RST   => REGFILE_HW_RST,   -- implement full hardware reset for register file
+    CPU_CLOCK_GATING_EN => CPU_CLOCK_GATING_EN,  -- enable clock gating when in sleep mode
+    CPU_FAST_MUL_EN     => CPU_FAST_MUL_EN,      -- use DSPs for M extension's multiplier
+    CPU_FAST_SHIFT_EN   => CPU_FAST_SHIFT_EN,    -- use barrel shifter for shift operations
+    CPU_REGFILE_HW_RST  => CPU_REGFILE_HW_RST,   -- implement full hardware reset for register file
     -- Hardware Performance Monitors (HPM) --
-    HPM_NUM_CNTS     => HPM_NUM_CNTS,     -- number of implemented HPM counters (0..13)
-    HPM_CNT_WIDTH    => HPM_CNT_WIDTH     -- total size of HPM counters
+    HPM_NUM_CNTS        => HPM_NUM_CNTS,     -- number of implemented HPM counters (0..13)
+    HPM_CNT_WIDTH       => HPM_CNT_WIDTH     -- total size of HPM counters
   )
   port map (
     -- global control --
@@ -298,9 +299,9 @@ begin
   -- -------------------------------------------------------------------------------------------
   neorv32_cpu_regfile_inst: entity neorv32.neorv32_cpu_regfile
   generic map (
-    RST_EN => REGFILE_HW_RST, -- enable dedicated hardware reset ("ASIC style")
-    RVE_EN => RISCV_ISA_E,    -- implement embedded RF extension
-    RS3_EN => rf_rs3_en_c     -- enable 3rd read port
+    RST_EN => CPU_REGFILE_HW_RST, -- enable dedicated hardware reset ("ASIC style")
+    RVE_EN => RISCV_ISA_E,        -- implement embedded RF extension
+    RS3_EN => rf_rs3_en_c         -- enable 3rd read port
   )
   port map (
     -- global control --
@@ -340,8 +341,8 @@ begin
     RISCV_ISA_Zmmul  => RISCV_ISA_Zmmul,  -- implement multiply-only M sub-extension
     RISCV_ISA_Zxcfu  => RISCV_ISA_Zxcfu,  -- implement custom (instr.) functions unit
     -- Tuning Options --
-    FAST_MUL_EN      => FAST_MUL_EN,      -- use DSPs for M extension's multiplier
-    FAST_SHIFT_EN    => FAST_SHIFT_EN     -- use barrel shifter for shift operations
+    FAST_MUL_EN      => CPU_FAST_MUL_EN,  -- use DSPs for M extension's multiplier
+    FAST_SHIFT_EN    => CPU_FAST_SHIFT_EN -- use barrel shifter for shift operations
   )
   port map (
     -- global control --