feature request - Zb* sub-extensions

[biosbob]

the Zbc sub-extension (carry-less multiplication) is quite different from the other sub-extensions, which really do "bit manipulation" in the more traditional sense...

not critical, but it might be helpful to enable the Zb* sub-extensions individual -- as this also has impact on the overall size of the synthesized core....

a placeholder for the future....

[stnolting]

For the records: this is being discussed in #633 (comment)

[biosbob]

#633 talks about the Zc* sub-extensions; this issue concerns the Zb* sub-extensions....

perhaps the data-sheet could not only list the extensions currently supported, but those on (or NOT on) the roadmap....

[stnolting]

Oh sorry, seems like I have mixed up something 😅

B vs. Zb* is something I need to take care of because the B extensions basically does not exist (anymore): riscv/riscv-bitmanip#183

So we should replace CPU_EXTENSION_RISCV_B by several CPU_EXTENSION_RISCV_Zb* generics to fine tune the bitmanip extension. Actually, this fine-grained tuning is already implemented:

neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd

Lines 74 to 79 in a5bf1c8

	-- Sub-extension configuration ----------------------------
	-- Note that this configurations does NOT effect the CPU's (illegal) instruction decoding logic!
	constant zbb_en_c : boolean := true;
	constant zba_en_c : boolean := true;
	constant zbc_en_c : boolean := true;
	constant zbs_en_c : boolean := true;

But theses switches are not propagated to the top nor to the control unit to check for legal/illegal instructions.

[stnolting]

The B ISA extension has been ratified in April 2024 (https://wiki.riscv.org/display/HOME/Ratified+Extensions). It consists of the Zba, Zbb and Zbs sub-extensions, which is/are implemented by the core (see #869). So I think this can be closed now.