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B ISA extensions only contains Zba + Zbb + Zbs #869

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merged 6 commits into from
Apr 4, 2024
Merged

B ISA extensions only contains Zba + Zbb + Zbs #869

merged 6 commits into from
Apr 4, 2024

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@stnolting stnolting commented Apr 4, 2024 •
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Finally, the RISC-V B ISA extension (bit manipulation) has been frozen and is about to be ratified.

Now, B only contains the Zba, Zbb and Zbs sub-extensions but not the Zbc sub-extension (carry-less multiplication). Find more information at https://jira.riscv.org/browse/RVS-2006?src=confmacro.

⚠️ Hence, this PR removes Zbc support from the CPU (for now).

@stnolting stnolting added risc-v compliance Modification to comply with official RISC-V specs. HW Hardware-related cleanup Clean-up the codebase labels Apr 4, 2024
@stnolting stnolting self-assigned this Apr 4, 2024
@stnolting stnolting marked this pull request as ready for review April 4, 2024 18:00
@stnolting stnolting merged commit d43f9af into main Apr 4, 2024
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@stnolting stnolting deleted the b_isa_extension branch April 4, 2024 19:24
@stnolting stnolting mentioned this pull request May 28, 2024
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cleanup Clean-up the codebase HW Hardware-related risc-v compliance Modification to comply with official RISC-V specs.
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