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🐛 fix B.CTZ decoding regression bug #1018

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merged 2 commits into from
Sep 14, 2024
Merged

🐛 fix B.CTZ decoding regression bug #1018

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4de6a5f
:bug: [control] fix CTZ decoding
stnolting Sep 14, 2024
8e748e5
[changelog] add v1.10.3.8
stnolting Sep 14, 2024
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 14.09.2024 | 1.10.3.8 | :bug: fix `b.ctz` instruction decoding (bug introduced in v1.10.3.6) | [#1018](https://github.com/stnolting/neorv32/pull/1018) |
| 14.09.2024 | 1.10.3.7 | :warning: rework RTL files / hierarchy | [#1017](https://github.com/stnolting/neorv32/pull/1017) |
| 13.09.2024 | 1.10.3.6 | cleanup and extend watchdog's reset-cause identification logic | [#1015](https://github.com/stnolting/neorv32/pull/1015) |
| 13.09.2024 | 1.10.3.5 | rtl code cleanups; minor CPU control optimizations | [#1014](https://github.com/stnolting/neorv32/pull/1014) |
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2 changes: 1 addition & 1 deletion rtl/core/neorv32_cpu_control.vhd
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Expand Up @@ -655,7 +655,7 @@ begin
-- BITMANIP instruction --
if CPU_EXTENSION_RISCV_B then -- implemented at all?
-- register-immediate operation --
if ((f7_v = "0110000") and (f3_v = "001") and ((f5_v = "00000") or (f5_v = "00000") or (f5_v = "00010") or (f5_v = "00100") or (f5_v = "00101"))) or -- CLZ, CTZ, CPOP, SEXT.[B/H]
if ((f7_v = "0110000") and (f3_v = "001") and ((f5_v = "00000") or (f5_v = "00001") or (f5_v = "00010") or (f5_v = "00100") or (f5_v = "00101"))) or -- CLZ, CTZ, CPOP, SEXT.[B/H]
((f7_v = "0110000") and (f3_v = "101")) or -- RORI
((f7_v = "0010100") and (f3_v = "101") and (f5_v = "00111")) or -- ORCB
((f7_v = "0100100") and (f3_v(1 downto 0) = "01")) or -- BCLRI / BEXTI
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2 changes: 1 addition & 1 deletion rtl/core/neorv32_package.vhd
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Expand Up @@ -29,7 +29,7 @@ package neorv32_package is

-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100307"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100308"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

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