🧪 [pmp] use time-multiplex approach #1105
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reducing hardware costs by ~50%
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Instruction dispatch (getting the next instruction word for execution) and load/store accesses cannot happen at the same time due to the multi-cycle architecture of the CPU. Therefore, checking PMP (physical memory protection) permissions of instruction fetch and load/store access in parallel brings no benefit. Actually, it is quite inefficient as the PMP needs to replicate all the logic to do two look-ups in parallel.
This PR changes the PMP architecture to use a time-multiplex approach. The actual PMP permission/region check is simplified to a single "issue" that is time-multiplexed between instruction and data access.
As always, any kind of feedback is highly appreciated.