stnolting · stnolting · Jan 7, 2025 · Jan 7, 2025 · Jan 7, 2025 · Jan 7, 2025
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 07.01.2025 | 1.10.8.9 | rtl edits and cleanups; add dedicated "core complex" wrapper (CPU + L1 caches + bus switch) | [#1144](https://github.com/stnolting/neorv32/pull/1144) | 
 | 04.01.2025 | 1.10.8.8 | :sparkles: add inter-core communication (ICC) for the SMP dual-core setup | [#1142](https://github.com/stnolting/neorv32/pull/1142) |
 | 03.01.2025 | 1.10.8.7 | :warning: :sparkles: replace `Zalrsc` ISA extensions (reservation-set operations) by `Zaamo` ISA extension (atomic read-modify-write operations) | [#1141](https://github.com/stnolting/neorv32/pull/1141) |
 | 01.01.2025 | 1.10.8.6 | :sparkles: :test_tube: add smp dual-core option | [#1135](https://github.com/stnolting/neorv32/pull/1135) |

diff --git a/docs/datasheet/overview.adoc b/docs/datasheet/overview.adoc
@@ -130,36 +130,36 @@ The root directory of the repository is considered the NEORV32 base or home fold
 
 .Folder Structure
 ...................................
-neorv32               - Project home folder
+neorv32                 - Project home folder
 │
-├docs                 - Project documentation
-│├datasheet           - AsciiDoc sources for the NEORV32 data sheet
-│├figures             - Figures and logos
-│├references          - Data sheets and RISC-V specs
-│├sources             - Sources for the images in 'figures/'
-│└userguide           - AsciiDoc sources for the NEORV32 user guide
+├-docs                  - Project documentation
+│ ├-datasheet           - AsciiDoc sources for the NEORV32 data sheet
+│ ├-figures             - Figures and logos
+│ ├-references          - Data sheets and RISC-V specs
+│ ├-sources             - Sources for the images in 'figures/'
+│ └-userguide           - AsciiDoc sources for the NEORV32 user guide
 │
-├rtl                  - VHDL sources
-│├core                - Core sources of the CPU & SoC
-│├processor_templates - Pre-configured SoC wrappers
-│├system_integration  - System wrappers and bridges for advanced connectivity
-│└test_setups         - Minimal test setup "SoCs" used in the User Guide
+├-rtl                   - VHDL sources
+│ ├-core                - Core sources of the CPU & SoC
+│ ├-processor_templates - Pre-configured SoC wrappers
+│ ├-system_integration  - System wrappers and bridges for advanced connectivity
+│ └-test_setups         - Minimal test setup "SoCs" used in the User Guide
 │
-├sim                  - Simulation files
+├-sim                   - Simulation files
 │
-└-sw                  - Software framework
-  ├bootloader         - Sources of the processor-internal bootloader
-  ├common             - Linker script, crt0.S start-up code and central makefile
-  ├example            - Example programs for the core and the SoC modules
-  │├eclipse           - Pre-configured Eclipse IDE project
-  │└...               - Several example programs
-  ├lib                - Processor core library
-  │├include           - NEORV32 core library header files (*.h)
-  │└source            - NEORV32 core library source files (*.c)
-  ├image_gen          - Helper program to generate executables & memory images
-  ├ocd_firmware       - Firmware for the on-chip debugger's "park loop"
-  ├openocd            - OpenOCD configuration files
-  └svd                - Processor system view description file (CMSIS-SVD)
+└-sw                    - Software framework
+  ├-bootloader          - Sources of the processor-internal bootloader
+  ├-common              - Linker script, crt0.S start-up code and central makefile
+  ├-example             - Example programs for the core and the SoC modules
+  │ ├-eclipse           - Pre-configured Eclipse IDE project
+  │ └-...               - Several example programs
+  ├-lib                 - Processor core library
+  │ ├-include           - NEORV32 core library header files (*.h)
+  │ └-source            - NEORV32 core library source files (*.c)
+  ├-image_gen           - Helper program to generate executables & memory images
+  ├-ocd_firmware        - Firmware for the on-chip debugger's "park loop"
+  ├-openocd             - OpenOCD configuration files
+  └-svd                 - Processor system view description file (CMSIS-SVD)
 ...................................
 
 
@@ -179,60 +179,61 @@ All core VHDL files from the list below have to be assigned to a **new library**
 [NOTE]
 See section <<_file_list_files>> for more information.
 
-.RTL File List and Hierarchy (in alphabetical order)
+.RTL File List (in alphabetical order)
 ...................................
-neorv32_top.vhd                 - NEORV32 PROCESSOR/SOC TOP ENTITY
-│
-├neorv32_cpu.vhd                - NEORV32 CPU TOP ENTITY
-│├neorv32_cpu_alu.vhd           - Arithmetic/logic unit
-││├neorv32_cpu_cp_bitmanip.vhd  - Bit-manipulation co-processor (B ext.)
-││├neorv32_cpu_cp_cfu.vhd       - Custom instructions co-processor (Zxcfu ext.)
-││├neorv32_cpu_cp_cond.vhd      - Integer conditional co-processor (Zicond ext.)
-││├neorv32_cpu_cp_crypto.vhd    - Scalar cryptographic co-processor (Zk*/Zbk* ext.)
-││├neorv32_cpu_cp_fpu.vhd       - Floating-point co-processor (Zfinx ext.)
-││├neorv32_cpu_cp_muldiv.vhd    - Mul/Div co-processor (M ext.)
-││└neorv32_cpu_cp_shifter.vhd   - Bit-shift co-processor (base ISA)
-│├neorv32_cpu_control.vhd       - CPU control, exception system and CSRs
-││└neorv32_cpu_decompressor.vhd - Compressed instructions decoder (C ext.)
-│├neorv32_cpu_icc.vhd           - Inter-core communication unit
-│├neorv32_cpu_lsu.vhd           - Load/store unit
-│├neorv32_cpu_pmp.vhd           - Physical memory protection unit (Smpmp ext.)
-│└neorv32_cpu_regfile.vhd       - Data register file
-│
-├neorv32_boot_rom.vhd           - Bootloader ROM
-│└neorv32_bootloader_image.vhd  - Bootloader ROM memory image (package)
-├neorv32_bus.vhd                - SoC bus infrastructure modules
-├neorv32_cache.vhd              - Generic cache module
-├neorv32_cfs.vhd                - Custom functions subsystem
-├neorv32_clint.vhd              - Core local interruptor
-├neorv32_clockgate.vhd          - Generic clock gating switch
-├neorv32_crc.vhd                - Cyclic redundancy check unit
-├neorv32_debug_dm.vhd           - on-chip debugger: debug module
-├neorv32_debug_auth.vhd         - on-chip debugger: authentication module
-├neorv32_debug_dtm.vhd          - on-chip debugger: debug transfer module
-├neorv32_dma.vhd                - Direct memory access controller
-├neorv32_dmem.vhd               - Generic processor-internal data memory
-├neorv32_fifo.vhd               - Generic FIFO component
-├neorv32_gpio.vhd               - General purpose input/output port unit
-├neorv32_gptmr.vhd              - General purpose 32-bit timer
-├neorv32_imem.vhd               - Generic processor-internal instruction memory
-│└neorv32_application_image.vhd - IMEM application initialization image (package)
-├neorv32_neoled.vhd             - NeoPixel (TM) compatible smart LED interface
-├neorv32_onewire.vhd            - One-Wire serial interface controller
-├neorv32_package.vhd            - Main VHDL package file
-├neorv32_pwm.vhd                - Pulse-width modulation controller
-├neorv32_sdi.vhd                - Serial data interface controller (SPI device)
-├neorv32_slink.vhd              - Stream link interface
-├neorv32_spi.vhd                - Serial peripheral interface controller (SPI host)
-├neorv32_sys.vhd                - System infrastructure modules
-├neorv32_sysinfo.vhd            - System configuration information memory
-├neorv32_trng.vhd               - True random number generator
-├neorv32_twi.vhd                - Two wire serial interface controller
-├neorv32_uart.vhd               - Universal async. receiver/transmitter
-├neorv32_wdt.vhd                - Watchdog timer
-├neorv32_xbus.vhd               - External (Wishbone) bus interface gateways
-├neorv32_xip.vhd                - Execute in place module
-└neorv32_xirq.vhd               - External interrupt controller
+rtl/core
+├-neorv32_application_image.vhd - IMEM application initialization image (package)
+├-neorv32_boot_rom.vhd          - Bootloader ROM
+├-neorv32_bootloader_image.vhd  - Bootloader ROM memory image (package)
+├-neorv32_bus.vhd               - SoC bus infrastructure modules
+├-neorv32_cache.vhd             - Generic cache module
+├-neorv32_clint.vhd             - Core local interruptor
+├-neorv32_clockgate.vhd         - Generic clock gating switch
+├-neorv32_cfs.vhd               - Custom functions subsystem
+├-neorv32_core_complex.vhd      - NEORV32 CORE COMPLEX TOP ENTITY
+├-neorv32_cpu.vhd               - NEORV32 CPU TOP ENTITY
+├-neorv32_cpu_alu.vhd           - Arithmetic/logic unit
+├-neorv32_cpu_control.vhd       - CPU control, exception system and CSRs
+├-neorv32_cpu_cp_bitmanip.vhd   - Bit-manipulation co-processor (B ext.)
+├-neorv32_cpu_cp_cfu.vhd        - Custom instructions co-processor (Zxcfu ext.)
+├-neorv32_cpu_cp_cond.vhd       - Integer conditional co-processor (Zicond ext.)
+├-neorv32_cpu_cp_crypto.vhd     - Scalar cryptography co-processor (Zk*/Zbk* ext.)
+├-neorv32_cpu_cp_fpu.vhd        - Floating-point co-processor (Zfinx ext.)
+├-neorv32_cpu_cp_muldiv.vhd     - Mul/Div co-processor (M ext.)
+├-neorv32_cpu_cp_shifter.vhd    - Bit-shift co-processor (base ISA)
+├-neorv32_cpu_decompressor.vhd  - Compressed instructions decoder (C ext.)
+├-neorv32_cpu_icc.vhd           - Inter-core communication unit
+├-neorv32_cpu_lsu.vhd           - Load/store unit
+├-neorv32_cpu_pmp.vhd           - Physical memory protection unit (Smpmp ext.)
+├-neorv32_cpu_regfile.vhd       - Data register file
+├-neorv32_crc.vhd               - Cyclic redundancy check unit
+├-neorv32_debug_auth.vhd        - On-chip debugger: authentication module
+├-neorv32_debug_dm.vhd          - On-chip debugger: debug module
+├-neorv32_debug_dtm.vhd         - On-chip debugger: debug transfer module
+├-neorv32_dma.vhd               - Direct memory access controller
+├-neorv32_dmem.vhd              - Generic processor-internal data memory
+├-neorv32_fifo.vhd              - Generic FIFO component
+├-neorv32_gpio.vhd              - General purpose input/output port unit
+├-neorv32_gptmr.vhd             - General purpose 32-bit timer
+├-neorv32_imem.vhd              - Generic processor-internal instruction memory
+├-neorv32_neoled.vhd            - NeoPixel (TM) compatible smart LED interface
+├-neorv32_onewire.vhd           - One-Wire serial interface controller
+├-neorv32_package.vhd           - Main VHDL package file
+├-neorv32_pwm.vhd               - Pulse-width modulation controller
+├-neorv32_sdi.vhd               - Serial data interface controller (SPI device)
+├-neorv32_slink.vhd             - Stream link interface
+├-neorv32_spi.vhd               - Serial peripheral interface controller (SPI host)
+├-neorv32_sys.vhd               - System infrastructure modules
+├-neorv32_sysinfo.vhd           - System configuration information memory
+├-neorv32_top.vhd               - NEORV32 PROCESSOR/SOC TOP ENTITY
+├-neorv32_trng.vhd              - True random number generator
+├-neorv32_twd.vhd               - Two wire serial device controller
+├-neorv32_twi.vhd               - Two wire serial interface controller
+├-neorv32_uart.vhd              - Universal async. receiver/transmitter
+├-neorv32_wdt.vhd               - Watchdog timer
+├-neorv32_xbus.vhd              - External (Wishbone) bus interface gateways
+├-neorv32_xip.vhd               - Execute in place module
+└-neorv32_xirq.vhd              - External interrupt controller
 ...................................
 
 .Replacing Modules for Customization or Optimization

diff --git a/rtl/core/neorv32_application_image.vhd b/rtl/core/neorv32_application_image.vhd
@@ -1,7 +1,7 @@
 -- The NEORV32 RISC-V Processor - github.com/stnolting/neorv32
 -- Auto-generated memory initialization image (for internal IMEM)
 -- Source: demo_blink_led/build/main.bin
--- Built: 04.01.2025 22:17:35
+-- Built: 07.01.2025 21:36:11
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -11,7 +11,7 @@ use neorv32.neorv32_package.all;
 
 package neorv32_application_image is
 
-constant application_init_size_c  : natural := 1248; -- bytes
+constant application_init_size_c  : natural := 1228; -- bytes
 constant application_init_image_c : mem32_t := (
 x"f14020f3",
 x"80002217",
@@ -23,11 +23,11 @@ x"000022b7",
 x"80028293",
 x"30029073",
 x"00000317",
-x"1a430313",
+x"19430313",
 x"30531073",
 x"30401073",
 x"00000397",
-x"4ac38393",
+x"49838393",
 x"80000417",
 x"fc440413",
 x"80000497",
@@ -37,7 +37,7 @@ x"fb450513",
 x"80000597",
 x"fac58593",
 x"00000617",
-x"1ac60613",
+x"19c60613",
 x"00000693",
 x"00000713",
 x"00000793",
@@ -57,31 +57,27 @@ x"00000e13",
 x"00000e93",
 x"00000f13",
 x"00000f93",
-x"06008263",
+x"04008a63",
 x"00000797",
 x"01878793",
 x"30579073",
 x"30446073",
 x"30046073",
-x"0f80006f",
+x"0e80006f",
 x"fff40737",
 x"00209793",
 x"00f70733",
 x"00072023",
-x"34202773",
-x"800007b7",
-x"00378793",
-x"02f71463",
 x"bc201073",
 x"bc0026f3",
 x"ffab4737",
 x"32170713",
-x"00d71a63",
+x"00d70463",
+x"30200073",
 x"bc171073",
 x"bc002173",
 x"bc002673",
-x"0580006f",
-x"30200073",
+x"0540006f",
 x"00838e63",
 x"00945c63",
 x"0003a783",
@@ -94,9 +90,9 @@ x"00052023",
 x"00450513",
 x"ff5ff06f",
 x"00000417",
-x"3a040413",
+x"39c40413",
 x"00000497",
-x"39848493",
+x"39448493",
 x"00945a63",
 x"00042083",
 x"000080e7",
@@ -116,9 +112,9 @@ x"30551073",
 x"f1402473",
 x"02041463",
 x"00000417",
-x"34840413",
+x"34440413",
 x"00000497",
-x"34048493",
+x"33c48493",
 x"00945a63",
 x"00042083",
 x"000080e7",
@@ -148,12 +144,12 @@ x"00000513",
 x"00000593",
 x"00112623",
 x"00812423",
-x"138000ef",
+x"140000ef",
 x"00000513",
 x"00150413",
 x"00000593",
 x"0ff57513",
-x"124000ef",
+x"12c000ef",
 x"0fa00513",
 x"038000ef",
 x"00040513",
@@ -170,49 +166,51 @@ x"c80025f3",
 x"fef59ae3",
 x"00008067",
 x"fe010113",
+x"01212823",
+x"fffe0937",
+x"00a12623",
+x"00092503",
+x"3e800593",
 x"00112e23",
 x"00812c23",
 x"00912a23",
-x"00a12623",
-x"0e0000ef",
-x"3e800593",
-x"1a8000ef",
+x"19c000ef",
 x"00c12603",
 x"00000693",
 x"00000593",
-x"0f8000ef",
+x"0ec000ef",
 x"00050413",
 x"00058493",
 x"fc0027f3",
 x"0807f793",
-x"04078463",
+x"04078663",
 x"320027f3",
 x"0017f793",
-x"02079e63",
-x"f9dff0ef",
+x"04079063",
+x"f95ff0ef",
 x"00850433",
 x"00a43533",
 x"009585b3",
 x"00b504b3",
-x"f89ff0ef",
+x"f81ff0ef",
 x"fe95eee3",
 x"00b49463",
 x"fe856ae3",
 x"01c12083",
 x"01812403",
 x"01412483",
+x"01012903",
 x"02010113",
 x"00008067",
-x"fffe07b7",
-x"0087a783",
+x"00892783",
 x"00f79713",
 x"02075663",
-x"f3dff0ef",
+x"f35ff0ef",
 x"00850433",
 x"00a43533",
 x"009585b3",
 x"00b504b3",
-x"f29ff0ef",
+x"f21ff0ef",
 x"fe95eee3",
 x"fcb490e3",
 x"fe856ae3",
@@ -230,9 +228,6 @@ x"fffc07b7",
 x"00a7a423",
 x"00b7a623",
 x"00008067",
-x"fffe07b7",
-x"0007a503",
-x"00008067",
 x"00050613",
 x"00000513",
 x"0015f693",