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RTL reworks, cleanups and optimizations #996

Merged
merged 16 commits into from
Aug 26, 2024
Merged

RTL reworks, cleanups and optimizations #996

merged 16 commits into from
Aug 26, 2024

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stnolting
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@stnolting stnolting commented Aug 25, 2024

  • Vivado IP module: major rework; use explicit std_logic[_vector] <-> std_ulogic[_vector] conversion; remove VHDL2008 requirement (not supported by the IP packager?)
  • CPU: remove reset of output register of multiplier unit to improve mapping to DSP block (FAST_MUL_EN option only)
  • CPU: ⚠️ remove user-level HPMs
  • CPU: rework mcountern CSR; add explicit CY and IR bits
  • CPU: rework "next PC" logic - use ALU adder to compute the next instruction address (removes one carry chain and shortens the critical path of the base CPU core)
  • DOCs: updates, cleanups and fixes

@stnolting stnolting added HW Hardware-related optimization Make things faster, smaller and more efficient cleanup Clean-up the codebase labels Aug 25, 2024
@stnolting stnolting self-assigned this Aug 25, 2024
@stnolting stnolting linked an issue Aug 25, 2024 that may be closed by this pull request
use "ALU.add = PC + IMM" with Imm=2/4 for computing the next PC (saves one adder and reduces input count of the next PC input multiplexer)
@stnolting stnolting marked this pull request as ready for review August 25, 2024 16:42
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@Sam-Vervaeck Sam-Vervaeck left a comment

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I had a look through all the changes, did not see anything weird.

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@Sam-Vervaeck Thanks for reviewing! :)

I'm still doing some (synthesis) tests, but everything seems to be fine so far.

@stnolting stnolting merged commit ea709d5 into main Aug 26, 2024
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@stnolting stnolting deleted the dev240824 branch August 26, 2024 18:25
@Sam-Vervaeck
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@stnolting This is still in the user guide but I think this pull request removed the need for this disclaimer in section 12?
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You are right! I forgot to remove that... Thanks for pointing that out!

stnolting added a commit that referenced this pull request Aug 28, 2024
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cleanup Clean-up the codebase HW Hardware-related optimization Make things faster, smaller and more efficient
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Typo in the IP block customisation
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