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RTL reworks, cleanups and optimizations #996
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to improve (Xilinx) DSP mapping (FAST_MUL option only)
std_ulogic[_vector] <-> std_logic[_vector]
- minor cleanups - add CSR reference link (doxagen) - add mcounteren defines
- mcounteren: add individual CY and IR bits - remove user-mode HPMs
use "ALU.add = PC + IMM" with Imm=2/4 for computing the next PC (saves one adder and reduces input count of the next PC input multiplexer)
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I had a look through all the changes, did not see anything weird.
@Sam-Vervaeck Thanks for reviewing! :) I'm still doing some (synthesis) tests, but everything seems to be fine so far. |
@stnolting This is still in the user guide but I think this pull request removed the need for this disclaimer in section 12? |
You are right! I forgot to remove that... Thanks for pointing that out! |
std_logic[_vector] <-> std_ulogic[_vector]
conversion; remove VHDL2008 requirement (not supported by the IP packager?)FAST_MUL_EN
option only)mcountern
CSR; add explicitCY
andIR
bits