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Handle csr mstatus and misa correctly #243

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merged 1 commit into from
Oct 7, 2023

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In the privileged arch-test, we need to set the extensions we used in the Machine ISA Register and set the Machine Status Register to privileged mode when we invoke the exception handler

In the privileged arch-test, we need to set the extensions we used in
the Machine ISA Register and set the Machine Status Register to
privileged mode when we invoke the exception handler
@jserv jserv merged commit 73ea55c into sysprog21:master Oct 7, 2023
vestata pushed a commit to vestata/rv32emu that referenced this pull request Jan 24, 2025
In the privileged section of the RISC-V Architecture Test, we must
configure the extensions specified in the Machine ISA (MISA) Register
and set the Machine Status Register to privileged mode when invoking
the exception handler.

With this commit, all tests have passed successfully.
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