Fix csrrc instruction behavior when rs1 is 0 #338
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According to the RISC-V specification, no write operation should occur when rs1 is equal to 0. The current implementation incorrectly clears all bits in the specified CSR. Introduces a fix that ensures the csrrc instruction refrains from performing any write operation when rs1 is 0.
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Jan 24, 2025
Fix csrrc instruction behavior when rs1 is 0
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According to the RISC-V specification, no write operation should occur when rs1 is equal to 0. The current implementation incorrectly clears all bits in the specified CSR.
Introduces a fix that ensures the csrrc instruction refrains from performing any write operation when rs1 is 0.