Skip to content
New issue

Have a question about this project? # for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “#”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? # to your account

Add support of FCLASS.S #47

Merged
merged 1 commit into from
Sep 4, 2022
Merged

Add support of FCLASS.S #47

merged 1 commit into from
Sep 4, 2022

Conversation

2011eric
Copy link
Collaborator

@2011eric 2011eric commented Sep 4, 2022

No description provided.

Copy link
Contributor

@jserv jserv left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Amend the git commit message to render the results of RISC-V Architectural Tests.

/* 0x080 rs1 is +INF */
out |= (f == 0x7f800000) ? 0x080 : 0;
out |= (expn == FMASK_EXPN && !frac && !sign) ? 0x080 : 0;
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Shall we update the description of these comments?

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

How should I update the description?

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Explicitly mentioning signedness checks would be better.

@2011eric
Copy link
Collaborator Author

2011eric commented Sep 4, 2022

Print the input and output of fclass:

static inline uint32_t calc_fclass(uint32_t f) {
  const uint32_t sign = f & FMASK_SIGN;
  const uint32_t expn = f & FMASK_EXPN;
  const uint32_t frac = f & FMASK_FRAC;

  /* TODO: optimize with a binary decision tree */

  uint32_t out = 0;
  /* 0x001    rs1 is -INF */
  out |= (f == 0xff800000) ? 0x001 : 0;
  /* 0x002    rs1 is negative normal */
  out |= (expn && (expn != FMASK_EXPN) && sign) ? 0x002 : 0;
  /* 0x004    rs1 is negative subnormal */
  out |= (!expn && frac && sign) ? 0x004 : 0;
  /* 0x008    rs1 is -0 */
  out |= (f == 0x80000000) ? 0x008 : 0;
  /* 0x010    rs1 is +0 */
  out |= (f == 0x00000000) ? 0x010 : 0;
  /* 0x020    rs1 is positive subnormal */
  out |= (!expn && frac && !sign) ? 0x020 : 0;
  /* 0x040    rs1 is positive normal */
  out |= (expn && (expn != FMASK_EXPN) && !sign) ? 0x040 : 0;
  /* 0x080    rs1 is +INF */
  out |= (expn == FMASK_EXPN && !frac && !sign) ? 0x080 : 0;
  /* 0x100    rs1 is a signaling NaN */
  out |= (expn == FMASK_EXPN && frac && !(frac & FMASK_QNAN)) ? 0x100 : 0;
  /* 0x200    rs1 is a quiet NaN */
  out |= (expn == FMASK_EXPN && (frac & FMASK_QNAN))? 0x200 : 0;

  printf("%08x ", f);
  printf("%08x\n", out);
  
  return out;
}
00000000 00000010
bf800000 00000002
3f800000 00000040
ffaaaaaa 00000100
7f800001 00000100
ffc55555 00000200
7fc00001 00000200
ffc00000 00000200
7fc00000 00000200
ff800000 00000001
7f800000 00000080
ff7fffff 00000002
7f7fffff 00000040
80855555 00000002
00800001 00000040
80800000 00000002
00800000 00000040
807fffff 00000004
007fffff 00000020
807ffffe 00000004
00000002 00000020
80000001 00000004
00000001 00000020
80000000 00000008
00000000 00000010
00000000 00000010
00000000 00000010
00000000 00000010
00000000 00000010
00000000 00000010
00000000 00000010
00000000 00000010
80000000 00000008
inferior exit code 0

@jserv
Copy link
Contributor

jserv commented Sep 4, 2022

Print the input and output of fclass:

Instead of dumping the difference in the signature, you should rewrite down the descriptive text in human-readable form. That is, you can summarize the riscv-arch-test reports.

There is a difference in the signature of fclass_b1-01.
When getting 0x80000000 as input, the expected output is 0x00000000, while our emulator output is 0x00000008.
However, in another testcase of the same input, the expected output is 0x00000008.
@jserv jserv merged commit e1dfd9c into sysprog21:master Sep 4, 2022
@jserv
Copy link
Contributor

jserv commented Sep 4, 2022

I amended the commit message, and further issues should be confirmed later.

vestata pushed a commit to vestata/rv32emu that referenced this pull request Jan 24, 2025
There is a difference in the signature of fclass_b1-01.
When getting 0x80000000 as input, the expected output is
0x00000000, while rv32emu generates 0x00000008. In
another test case of the same input, the expected output is
0x00000008.
# for free to join this conversation on GitHub. Already have an account? # to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants