Decouple instruction decoding from emulation unit #79
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This pull request introduces 1 alert when merging 244e3a3 into a550597 - view on LGTM.com new alerts:
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jserv
changed the title
src/decode.c
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| #include "decode.h" | ||
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| static inline bool decode_load(struct rv_insn_t *rv_insn, uint32_t insn) |
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I am not sure if it makes sense to give each instruction a single decode function. Since the same type of instruction (e.g. I-type, S-type, ...) should share the same decoding logic. I think that dealing with each instruction with an independent function introduces a lot of mess.
What you should do is define every type of decoding function, for example:
static inline bool decode_i_type(struct rv_insn_t *rv_insn, uint32_t insn)
{
/* I-type
* 31 20 19 15 14 12 11 7 6 0
* | imm[11:0] | rs1 | funct3 | rd | opcode |
*/
rv_insn->imm = dec_itype_imm(insn);
rv_insn->rs1 = dec_rs1(insn);
rv_insn->funct3 = dec_funct3(insn);
rv_insn->rd = dec_rd(insn);
}After that, you can fix the jump table or the label for compute-goto to jump to the correct types of decoding functions.
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Thanks for your reminder! I think I will try to rewrite as following for every instruction type
static inline bool op_load(struct rv_insn_t *ir, uint32_t insn)
{
/* decode I-type */
decode_i_type(ir, insn);
/* dispatch operation type */
switch (ir->funct3) {
...
}
return true;
}
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@Risheng1128, During code review, you should address the suggested improvements rather than simply responding "Thanks" as spam. That is, "show me the code" or response with something conceptual, which is ALWAYS better than nothing.
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riscv-arch-test result: RV32IMC and privilege situations pass. TODO:
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This pull request introduces 1 alert and fixes 1 when merging 11f02d5 into 3305664 - view on LGTM.com new alerts:
fixed alerts:
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This commit breaks RISC-V instruction decoding and emulation into separate
stage, meaning that it is feasible to incorporate further IR optimizations
and JIT code generation.
RISC-V Architecture Test: RV32I/M/C/privilege pass.
To implement jit compiler in emulator, need to separate the part of decode instruction from execution because we have to fetch instructions continuously.