Fix top testbench VERILOG_SOURCES

teobiton · Jan 27, 2024 · 0799bcf · 0799bcf
1 parent bc5e930
commit 0799bcf
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/tb/Makefile b/tb/Makefile
@@ -23,7 +23,7 @@ CORE_DIRECTORY = $(HW_DIRECTORY)/$(TOPLEVEL)
 CORE_SOURCES := $(shell cat $(CORE_DIRECTORY)/Flist.$(TOPLEVEL))
 
 # Pointing to the verilog files to test
-VERILOG_SOURCES = $(addprefix $(ROOT_DIRECTORY)/, $(CORE_SOURCES)) $(ITF_DIRECTORY)/simple_reg_interface.sv
+VERILOG_SOURCES = $(addprefix $(ROOT_DIRECTORY)/, $(CORE_SOURCES))
 
 # Verilator extra arguments to build waves
 EXTRA_ARGS += --trace --trace-structs --trace-fst