Generate waves to FST format by default

This format is better supported by gtkwave and allows enums values to keep their string name when represented.
teobiton · Jan 26, 2024 · 557037b · 557037b
1 parent 63fc12b
commit 557037b
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Showing 9 changed files with 9 additions and 8 deletions.
diff --git a/tb/.gitignore b/tb/.gitignore
@@ -3,4 +3,5 @@ __pycache__/
 sim_build/
 
 *.vcd
+*.fst
 *.xml
diff --git a/tb/Makefile b/tb/Makefile
@@ -26,7 +26,7 @@ CORE_SOURCES := $(shell cat $(CORE_DIRECTORY)/Flist.$(TOPLEVEL))
 VERILOG_SOURCES = $(addprefix $(ROOT_DIRECTORY)/, $(CORE_SOURCES)) $(ITF_DIRECTORY)/simple_reg_interface.sv
 
 # Verilator extra arguments to build waves
-EXTRA_ARGS += --trace --trace-structs
+EXTRA_ARGS += --trace --trace-structs --trace-fst
 
 include $(shell cocotb-config --makefiles)/Makefile.sim
 
diff --git a/tb/interface/makefile b/tb/interface/makefile
@@ -26,7 +26,7 @@ VERILOG_SOURCES = $(ITF_DIRECTORY)/$(VERILOG_FILE)
 ITERATIONS := 10 # Number of random tests ran
 
 # Verilator extra arguments to build waves
-EXTRA_ARGS += --trace --trace-structs
+EXTRA_ARGS += --trace --trace-structs --trace-fst
 
 include $(shell cocotb-config --makefiles)/Makefile.sim
 

diff --git a/tb/interface/test_simple_interface.py b/tb/interface/test_simple_interface.py
@@ -253,7 +253,7 @@ def test_interface_regs(DataWidth, BlockWidth, ByteAlign, DigestWidth):
     extra_args: List[str] = []
 
     if SIM == "verilator" and WAVES == "1":
-        extra_args = ["--trace", "--trace-structs"]
+        extra_args = ["--trace", "--trace-structs", "--trace-fst"]
 
     parameters: Dict[str, str] = {}
 

diff --git a/tb/sha1/makefile b/tb/sha1/makefile
@@ -22,6 +22,6 @@ MODULE = test_sha1_core
 VERILOG_SOURCES = $(SHA_DIRECTORY)/sha1_core.sv
 
 # Verilator extra arguments to build waves
-EXTRA_ARGS += --trace --trace-structs
+EXTRA_ARGS += --trace --trace-structs --trace-fst
 
 include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/tb/sha1/test_sha1_core.py b/tb/sha1/test_sha1_core.py
@@ -264,7 +264,7 @@ def test_sha1_core():
     extra_args: List[str] = []
 
     if SIM == "verilator" and WAVES == "1":
-        extra_args = ["--trace", "--trace-structs"]
+        extra_args = ["--trace", "--trace-structs", "--trace-fst"]
 
     parameters: Dict[str, str] = {}
 

diff --git a/tb/sha2/makefile b/tb/sha2/makefile
@@ -22,7 +22,7 @@ MODULE = test_sha2_cores
 VERILOG_SOURCES = $(SHA_DIRECTORY)/sha256_core.sv
 
 # Verilator extra arguments to build waves
-EXTRA_ARGS += --trace --trace-structs
+EXTRA_ARGS += --trace --trace-structs --trace-fst
 
 include $(shell cocotb-config --makefiles)/Makefile.sim
 
diff --git a/tb/sha2/test_sha2_cores.py b/tb/sha2/test_sha2_cores.py
@@ -287,7 +287,7 @@ def test_sha256_core(core, DigestWidth):
     extra_args: List[str] = []
 
     if SIM == "verilator" and WAVES == "1":
-        extra_args = ["--trace", "--trace-structs"]
+        extra_args = ["--trace", "--trace-structs", "--trace-fst"]
 
     parameters: Dict[str, str] = {}
 

diff --git a/tb/test_tops.py b/tb/test_tops.py
@@ -373,7 +373,7 @@ def test_ip(ip, DigestWidth):
     extra_args: List[str] = []
 
     if SIM == "verilator" and WAVES == "1":
-        extra_args = ["--trace", "--trace-structs"]
+        extra_args = ["--trace", "--trace-structs", "--trace-fst"]
 
     parameters: Dict[str, str] = {}
-Original file line number
+Diff line change
@@ Expand Up / @@ -3,4 +3,5 @@ __pycache__/ @@
     sim_build/
     *.vcd
+    *.fst
     *.xml