Extremely basic CortexM0 SoC based on ARM DesignStart Eval
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Updated
Oct 8, 2018 - Verilog
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
This is a replica made in Verilog language data flow of the ARM processor Cortex M0 with Instruction Set Architecture based in ARMv6. Although this is far from being the same, specially in the memory part, the functionality and usability its the most aproximate we could get in a Zybo Z7-10 in the small time space I had to do this. (UNFINISHED)
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