draws an SVG schematic from a JSON netlist

HAL – The Hardware Analyzer

PCB Design Language: A programming way to design schematics.

Tools for working with circuits as graphs in python

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Structural Netlist API (and more) for EDA post synthesis flow development

A mixed signal netlist language (pre-alpha)

A standalone structural (gate-level) verilog parser

A hand-drawn schematic sketch recognizer and converter. Traditional object detection techniques built using OpenCV; deep learning classification powered by TensorFlow 2 using the Keras API.

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

SPICE netlists parser for .NET

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

This is a demo for still image compression application

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

A low-level hierarchical netlist assembler for FPGAs

Benchmark suite for HAL

This is a SpyDrNet Plugin for a physical design related transformations

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

SKiDL Microcontroller Board Wizard

TMR utilities for the SpyDrNet project