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phase-locked-loop

Here are 5 public repositories matching this topic...

manili / VSDBabySoC

VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

risc-v mixed-signal system-on-chip digital-to-analog-converter phase-locked-loop rvmyth

Updated Jan 4, 2022
Verilog

lakshmi-sathi / avsdpll1v8_caravel

PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC

130nm open-mpw google-skywater-pdk phase-locked-loop

Updated Dec 8, 2020
Verilog

antonysigma / femptosecond-pulse-trigger-pcb

Extract the 15MHz clock signal from 400 picosecond pulse train

clock-synchronization ultrafast-optics microwave-filters phase-locked-loop mode-locked-laser

Updated May 4, 2023
GLSL

DericAugusto / ISN2022_InfTransmission

Material from the course of Information Transmission at ENSEM - Université de Lorraine.

entropy huffman-coding telecommunications channel-coding qam-modulation bit-error-rate source-coding phase-locked-loop

Updated Sep 17, 2023
MATLAB

Ernane-AAC / Arduino-PLL

This repository shows how to implement a simple PLL and a Frequency Meter using Arduino Uno.

phase-locked-loop frequency-meter arduino-pll sine-lookup-table pwm-analog-output

Updated Aug 28, 2024
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