A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

Sequential & Pipelined implementation of Y86-64 ISA in Verilog

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor