This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.
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Nov 9, 2024 - C++
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pynq-z2
Here are 44 public repositories matching this topic...
Low Precision(quantized) Yolov5
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Jan 28, 2024 - Python
Low-Precision YOLO on PYNQ with FINN
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Nov 26, 2023 - Jupyter Notebook
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Nov 30, 2018
MNIST accelerator using binary qunatization on Xilinx pynq-z2
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Sep 4, 2024 - C++
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
python zynq jupyter-notebook xilinx uart pynq pynq-hardware-overlay xilinx-fpga icap xilinx-vivado axi pynq-z1 pynq-z2 soft-error sem-ip
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May 1, 2020 - Tcl
FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)
python fpga deep-learning neural-network tensorflow keras cnn mnist verilog vivado ps pynq cnn-keras pl mnist-handwriting-recognition pynq-z2 programmable-logic processing-system
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Dec 12, 2023 - VHDL
tensorflor 2.1 wheel for pynq z2 ( zynq 7000 xilinx SoC ), cross compiled with different compiler's flags using the script provided by tensorflow for building it for rasberry
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Jun 22, 2020 - Shell
A Verilog implementation of a hand-written digit recognition Neural Network
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Nov 16, 2024 - Jupyter Notebook
Hardware Accelerator for ML
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May 29, 2024 - VHDL
A fast and efficient implementation of a SHA256 cracker
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May 17, 2020 - VHDL
MSc Final Project
embedded vhdl embedded-systems bare-metal msc-project embedded-c msc-thesis zynq-7000 custom-development lcd-driver bare-metal-programming pynq-z2 custom-font
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Jan 10, 2022 - C
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
sdk fpga hardware accelerator matrix project matrix-multiplication verilog xilinx vivado systemverilog hardware-designs hdl hardware-acceleration zynq-7000 systolic-arrays pynq-z2 vitis
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Feb 16, 2024 - SystemVerilog
Repository that contains some neural network inferences on PYNQ-Z2 board employing hls4ml
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Dec 22, 2021 - Ada
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Jan 24, 2019 - C++
This project automates process of creating a PYNQ Z1/Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
python automation fpga vhdl verilog xilinx vivado hardware-designs pynq hdl pynq-z1 pynq-z2 pynq-platform hdlgen-chatgpt
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Jan 28, 2025 - Python
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