sdram

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cw1997 / SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

hardware systemverilog hardware-designs sdram sdram-controller verilog-project

Updated Jul 1, 2022
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sdram

Here is 1 public repository matching this topic...

cw1997 / SDRAM-Controller

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