Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis
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Updated
Dec 9, 2022 - AGS Script
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sram-cell
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This project demonstrates the **design of a 6-Transistor (6T) SRAM memory cell** using the **Electric VLSI Design System**. It includes only the **schematic and layout**—simulation and waveform outputs are not included in this repository.
open-source memory schematic free vlsi cmos circuit-design vlsi-design sram-cell layout-design electric-vlsi
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Updated
May 11, 2025
This project demonstrates the **design of a 6-Transistor (6T) SRAM memory cell** using the **Electric VLSI Design System**. It includes only the **schematic and layout**—simulation and waveform outputs are not included in this repository.
open-source memory schematic free vlsi cmos circuit-design vlsi-design sram-cell layout-design electric-vlsi
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Updated
May 17, 2025
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