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terasic-de10-standard

Here are 4 public repositories matching this topic...

MinhTran0911 / DS1302_Interface_DE10

DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA

ds1302 systemverilog hdl modelsim quartus-prime cyclone-v rtc-module hardware-description-language altera-fpga terasic-de10-standard

Updated Jul 30, 2022
SystemVerilog

MinhTran0911 / UART_DE10

UART Receiver and Transmitter using Terasic DE-10 Standard FPGA

uart systemverilog hdl modelsim quartus-prime hardware-description-language altera-fpga terasic-de10-standard

Updated Aug 4, 2022
SystemVerilog

MinhTran0911 / Stopwatch_DE10

Basic Stopwatch Design using Terasic DE-10 Standard FPGA

systemverilog hdl modelsim quartus-prime cyclone-v hardware-description-language altera-fpga terasic-de10-standard

Updated Jul 30, 2022
SystemVerilog

MinhTran0911 / Simple_CPU_DE10

Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA

cpu fpga systemverilog hdl modelsim quartus-prime cyclone-v hardware-description-language altera-fpga terasic-de10-standard

Updated Aug 3, 2022
SystemVerilog

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