Inference Design, Behavioral simulations, and Hardware Implementation.
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May 26, 2021 - Verilog
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xilinx-zynq
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The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
fpga processor image-processing microprocessor datapath risc hardware-acceleration softcore xilinx-zynq pipelined-processors ippro
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Feb 14, 2023 - Verilog
Microarquitecturas y Softcores - CESE - FIUBA
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Dec 13, 2023 - Verilog
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