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Loopy is a framework to automatically establish connections from high-level software languages like C++ or Java to hardware devices implemented in an FPGA. Loopy has a modular structure and provides a unified generator framework with exchangeable
- host languages,
- evaluation boards and FPGA types,
- communication media such as Ethernet, PCIe, or USB, and
- FPGA synthesis workflows.
Loopy is open source and freely available to everyone. It is maintained by the Microelectronic Systems Design Research Group and the Software Technology Group at the University of Kaiserslautern, Germany. However, contributions in any kinds are warmly welcome from everyone.
- C++ host backend
- Xilinx ISE synthesis backend
- Xilinx ML-605 evaluation board
- Ethernet connections
See our roadmap for planned extensions.
Loopy has been presented for the first time at the ReConFig conference 2013 in Cancún. Access the paper here.
Setting up host-to-board connections for hardware validation or hybrid simulation purposes is a time-consuming and error-prone process. In this paper we present a novel approach to automatically generate host-to-board connections, called the Loopy framework. The generated drivers enable blocking and non-blocking access to the hardware from high-level languages like C++ through an intuitive, object-based model of the hardware implementation. The framework itself is written in Java, and offers cross-platform support. It is open-source, well-documented, and can be enhanced with new supported languages, boards, tools, and features easily. Loopy combines several approaches presented in the past to an all-embracing helper toolkit for hardware designers, verification engineers, or people who want to use hardware accelerators in a software context. We have evaluated Loopy with real-life examples and present a case study with a complex MIMO system hardware-in-the-Ioop setup.