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remove switchboard submodule and use switchboard-hw only #121

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merged 1 commit into from
Feb 16, 2024
+8 −27
Merged

remove switchboard submodule and use switchboard-hw only #121

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3 changes: 0 additions & 3 deletions .gitmodules
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Original file line number Diff line number Diff line change
@@ -1,6 +1,3 @@
[submodule "submodules/lambdalib"]
path = submodules/lambdalib
url = git@github.com:siliconcompiler/lambdalib.git
[submodule "submodules/switchboard"]
path = submodules/switchboard
url = git@github.com:zeroasiccorp/switchboard.git
2 changes: 0 additions & 2 deletions lumi/testbench/test_lumi.py
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Original file line number Diff line number Diff line change
Expand Up @@ -27,11 +27,9 @@ def build_testbench(topo="2d", trace=False):
else:
raise ValueError('Invalid topology')

dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
for option in ['ydir', 'idir']:
dut.add('option', option, EX_DIR / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'umi' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
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2 changes: 0 additions & 2 deletions lumi/testbench/test_lumi_rnd.py
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Original file line number Diff line number Diff line change
Expand Up @@ -27,11 +27,9 @@ def build_testbench(topo="2d", trace=False):
else:
raise ValueError('Invalid topology')

dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
for option in ['ydir', 'idir']:
dut.add('option', option, EX_DIR / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'umi' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
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1 change: 0 additions & 1 deletion submodules/switchboard
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Submodule switchboard deleted from dd5a7b
4 changes: 1 addition & 3 deletions umi/testbench/test_crossbar.py
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Original file line number Diff line number Diff line change
Expand Up @@ -14,18 +14,16 @@
THIS_DIR = Path(__file__).resolve().parent

def build_testbench():
dut = SbDut('testbench')
dut = SbDut('testbench', default_main=True)

EX_DIR = Path('..')
EX_DIR = EX_DIR.resolve()

# Set up inputs
dut.input('testbench_crossbar.sv')

dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
for option in ['ydir', 'idir']:
dut.add('option', option, EX_DIR / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
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4 changes: 1 addition & 3 deletions umi/testbench/test_fifo.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,18 +13,16 @@


def build_testbench():
dut = SbDut('testbench')
dut = SbDut('testbench', default_main=True)

EX_DIR = Path('..')
EX_DIR = EX_DIR.resolve()

# Set up inputs
dut.input('testbench_fifo.sv')

dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
for option in ['ydir', 'idir']:
dut.add('option', option, EX_DIR / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
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4 changes: 1 addition & 3 deletions umi/testbench/test_fifo_flex.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,18 +13,16 @@


def build_testbench():
dut = SbDut('testbench')
dut = SbDut('testbench', default_main=True)

EX_DIR = Path('..')
EX_DIR = EX_DIR.resolve()

# Set up inputs
dut.input('testbench_fifo_flex.sv')

dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
for option in ['ydir', 'idir']:
dut.add('option', option, EX_DIR / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
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4 changes: 1 addition & 3 deletions umi/testbench/test_mem_agent.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,18 +13,16 @@


def build_testbench():
dut = SbDut('testbench')
dut = SbDut('testbench', default_main=True)

EX_DIR = Path('..')
EX_DIR = EX_DIR.resolve()

# Set up inputs
dut.input('testbench_mem_agent.sv')

dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
for option in ['ydir', 'idir']:
dut.add('option', option, EX_DIR / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
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4 changes: 1 addition & 3 deletions umi/testbench/test_regif.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,18 +13,16 @@


def build_testbench():
dut = SbDut('testbench')
dut = SbDut('testbench', default_main=True)

EX_DIR = Path('..')
EX_DIR = EX_DIR.resolve()

# Set up inputs
dut.input('testbench_regif.sv')

dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
for option in ['ydir', 'idir']:
dut.add('option', option, EX_DIR / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl')
dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl')
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2 changes: 1 addition & 1 deletion utils/testbench/test_umi2tl_np.py
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Expand Up @@ -11,7 +11,7 @@


def build_testbench(topo="2d"):
dut = SbDut('testbench')
dut = SbDut('testbench', default_main=False)

EX_DIR = Path('../..')
EX_DIR = EX_DIR.resolve()
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3 changes: 1 addition & 2 deletions utils/testbench/test_umi_address_remap.py
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@


def build_testbench(topo="2d"):
dut = SbDut('testbench')
dut = SbDut('testbench', default_main=True)

EX_DIR = Path('../..')

Expand All @@ -26,7 +26,6 @@ def build_testbench(topo="2d"):
else:
raise ValueError('Invalid topology')

dut.input(EX_DIR / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc')
for option in ['ydir', 'idir']:
dut.add('option', option, EX_DIR / 'umi' / 'rtl')
dut.add('option', option, EX_DIR / 'utils' / 'rtl')
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2 changes: 1 addition & 1 deletion utils/testbench/test_umi_packet_merge_greedy.py
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@


def build_testbench(topo="2d"):
dut = SbDut('testbench')
dut = SbDut('testbench', default_main=False)

EX_DIR = Path('../..')

Expand Down