Merge pull request #10525 from g-w1/plan9-zig-test

Plan9 zig test
ziglang · Jan 9, 2022 · d66c97d · d66c97d
2 parents 2a39d80 + 398c0b1
commit d66c97d
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Showing 3 changed files with 35 additions and 3 deletions.
diff --git a/src/arch/x86_64/Isel.zig b/src/arch/x86_64/Isel.zig
@@ -753,7 +753,16 @@ fn dbgAdvancePCAndLine(isel: *Isel, line: u32, column: u32) InnerError!void {
             const d_pc_p9 = @intCast(i64, delta_pc) - quant;
             if (d_pc_p9 > 0) {
                 // minus one because if its the last one, we want to leave space to change the line which is one quanta
-                try dbg_out.dbg_line.append(@intCast(u8, @divExact(d_pc_p9, quant) + 128) - quant);
+                var diff = @divExact(d_pc_p9, quant) - quant;
+                while (diff > 0) {
+                    if (diff < 64) {
+                        try dbg_out.dbg_line.append(@intCast(u8, diff + 128));
+                        diff = 0;
+                    } else {
+                        try dbg_out.dbg_line.append(@intCast(u8, 64 + 128));
+                        diff -= 64;
+                    }
+                }
                 if (dbg_out.pcop_change_index.*) |pci|
                     dbg_out.dbg_line.items[pci] += 1;
                 dbg_out.pcop_change_index.* = @intCast(u32, dbg_out.dbg_line.items.len - 1);

diff --git a/src/link.zig b/src/link.zig
@@ -643,7 +643,7 @@ pub const File = struct {
             .coff => return @fieldParentPtr(Coff, "base", base).getDeclVAddr(decl),
             .elf => return @fieldParentPtr(Elf, "base", base).getDeclVAddr(decl),
             .macho => return @fieldParentPtr(MachO, "base", base).getDeclVAddr(decl),
-            .plan9 => @panic("GET VADDR"),
+            .plan9 => return @fieldParentPtr(Plan9, "base", base).getDeclVAddr(decl),
             .c => unreachable,
             .wasm => unreachable,
             .spirv => unreachable,

diff --git a/src/link/Plan9.zig b/src/link/Plan9.zig
@@ -203,7 +203,7 @@ fn putFn(self: *Plan9, decl: *Module.Decl, out: FnDeclOutput) !void {
         self.syms.items[fn_map_res.value_ptr.sym_index] = .{
             .type = .z,
             // just put a giant number, no source file will have this many newlines
-            .value = std.math.maxInt(u32),
+            .value = std.math.maxInt(u31),
             .name = &.{ 0, 0 },
         };
     }
@@ -740,3 +740,26 @@ pub fn allocateDeclIndexes(self: *Plan9, decl: *Module.Decl) !void {
     _ = self;
     _ = decl;
 }
+pub fn getDeclVAddr(self: *Plan9, decl: *const Module.Decl) u64 {
+    if (decl.ty.zigTypeTag() == .Fn) {
+        var start = self.bases.text;
+        var it_file = self.fn_decl_table.iterator();
+        while (it_file.next()) |fentry| {
+            var symidx_and_submap = fentry.value_ptr;
+            var submap_it = symidx_and_submap.functions.iterator();
+            while (submap_it.next()) |entry| {
+                if (entry.key_ptr.* == decl) return start;
+                start += entry.value_ptr.code.len;
+            }
+        }
+        unreachable;
+    } else {
+        var start = self.bases.data + self.got_len * if (!self.sixtyfour_bit) @as(u32, 4) else 8;
+        var it = self.data_decl_table.iterator();
+        while (it.next()) |kv| {
+            if (decl == kv.key_ptr.*) return start;
+            start += kv.value_ptr.len;
+        }
+        unreachable;
+    }
+}