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Enable SVE Support for L2 Metric Computation in FP32 #969
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Welcome @adarshs1310! It looks like this is your first PR to zilliztech/knowhere 🎉 |
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svbool_t pg = svptrue_b32(); | ||
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while (i < d) { | ||
if (d - i < svcntw()) |
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I believe that this if
condition is not needed, just pg = svwhilelt_b32(i, d);
should be sufficient
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Thank you so much, @alexanderguzhva , for the valuable suggestions. During development, we considered this approach as well, and our reason for going with the current approach is as follows:
Using the if condition to update pg only in the last iteration avoids unnecessary updates and reduces the dependency chain introduced by the svwhilelt instruction. This optimization minimizes stalls caused by these dependencies, allowing the processor pipeline to operate more efficiently.
cmake/libs/libfaiss.cmake
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@@ -48,7 +48,7 @@ endif() | |||
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if(__AARCH64) | |||
set(UTILS_SRC src/simd/hook.cc src/simd/distances_ref.cc | |||
src/simd/distances_neon.cc) | |||
src/simd/distances_neon.cc src/simd/distances_sve.cc) |
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I believe that this is not sufficient.
Knowhere is designed as a library that picks function pointers according to CPU capabilities, detected upon the start.
For example, SSE / AVX2 / AVX512 code files have different corresponding compile options
knowhere/cmake/libs/libfaiss.cmake
Lines 37 to 40 in 1cb9937
target_compile_options(utils_sse PRIVATE -msse4.2 -mpopcnt) | |
target_compile_options(utils_avx PRIVATE -mfma -mf16c -mavx2 -mpopcnt) | |
target_compile_options(utils_avx512 PRIVATE -mfma -mf16c -mavx512f -mavx512dq | |
-mavx512bw -mpopcnt -mavx512vl) |
So, it seems to be logical that the new SVE code should also contain some form of different flags, such as -march=armv8-a+sve
for distances_sve.cc
. And I don't believe that I see this.
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Thank you for your valuable feedback @alexanderguzhva
We considered two approaches: first, to keep Neon as the default until all FP32 functions for SVE have been fully implemented. Based on this, we decided to proceed with this approach.
Your approach is absolutely correct, and we agree that the Neon fallback for non-SVE functions can be effectively handled using hook.cc.
We have incorporated these changes into our solution.
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@alexanderguzhva @foxspy @hhy3 Requesting updates to the CI pipeline to address GCC header file conflicts. Since Ubuntu 22.04 defaults to GCC-11, there is a risk of incorrect header usage when GCC-12 is installed. To resolve this, the GCC-11 header files should be removed after installing GCC-12. The necessary changes have been incorporated into the ARM-based Ubuntu 22.04 Docker configuration as part of this PR, ensuring proper SVE compatibility. Kindly review and consider these adjustments for consistent and accurate builds. Thank you! |
/kind feature |
Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #969 +/- ##
=========================================
+ Coverage 0 73.12% +73.12%
=========================================
Files 0 86 +86
Lines 0 8542 +8542
=========================================
+ Hits 0 6246 +6246
- Misses 0 2296 +2296 🚀 New features to boost your workflow:
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@adarshs1310 would you please rebase on top of master? it contains a fix for UT. Thanks. |
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Sure @alexanderguzhva! The rebase has been done now! |
Hi @alexanderguzhva , @foxspy , @hhy3 , Could you please look into the SSE fix when you have a chance? The ARM CI issue has already been handled in our code. Thank you so much for your support! |
SSE's CI will not block; but ARM's CI fails |
@adarshs1310 I was able to compile and run knowhere on AWS Graviton 3 using GCC-12. I see the following error during unit tests, which seems to be a minor precision issue. Still, would you be able to find the root of this problem?
Other unit tests pass. The compilation is the following (given that you have created a profile for GCC 12 for conan): mkdir build
cd build
conan install .. --build=missing -o with_diskann=True -o with_ut=True -o with_benchmark=True -s compiler.libcxx=libstdc++11 -c tools.build:cxxflags+=[\"-mcpu=neoverse-512tvb\",\"-march=native\"] -s build_type=Release --profile=gcc12
conan build .. |
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Hi @presburger, kindly support us to check the above 2 failing checks they seem to be independent of our changes and please support us to merge the PR. |
@presburger @foxspy @alexanderguzhva, Can we please look this up at priority? We have our development ready for FP16 L2 and IP functions and we are looking to contribute as and when this is done. |
/lgtm |
As long as the CI passes, I'll merge this PR. |
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New changes are detected. LGTM label has been removed. |
@presburger Thank you for your reply, all my test cases are passing except for the one quoted in the issue #1100, which is failing even on the main branch, can we please look into this at priority. CI issue is not at our end. |
@alexanderguzhva @foxspy @presburger Output is truncated here, can you please help me with it, what is this issue, is it only related to #1100 or do I need to fix something at my end as well. |
@adarshs1310 I've tried rebasing your PR on top fo the current master, and all uts seems to pass on AWS graviton 3. Please confirm. Thanks. |
Signed-off-by:Adarsh Srivastava <adarsh.srivastava@fujitsu.com> Signed-off-by: Adarsh Srivastava <Adarsh.Srivastava@fujitsu.com>
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[APPROVALNOTIFIER] This PR is APPROVED This pull-request has been approved by: adarshs1310, presburger The full list of commands accepted by this bot can be found here. The pull request process is described here
Needs approval from an approver in each of these files:
Approvers can indicate their approval by writing |
@alexanderguzhva Thanks for looking into it, I have rebased and pushed the changes. |
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@alexanderguzhva @presburger Gentle Reminder! CI seems to be an issue at your end as discussed with @alexanderguzhva, all uts are passing on Graviton3 machines. |
@alexanderguzhva @presburger @foxspy Can you please share what is the issue? All the uts are passing but some test in jenkins is failing? |
Description:
This PR introduces SVE (Scalable Vector Extension) enablement for L2 metric computation in FP32. The changes enhance performance for most indexing methods compared to NEON, with observed speed-ups across multiple algorithms.
Changes in This PR:
Benchmark Results:
Performance benchmarks(32 vcpus) were conducted using both NEON and SVE on ARM architecture. Below are the results showcasing execution times (in seconds):
Key observations:
Note: SVE support has been made optional, as not all functions have been fully enabled yet. To utilize SVE, please compile with -march=armv8-a+sve.
/kind feature
Fixes #782