WIP on new core code

vhdmmio/config/conditions.py

@@ -1,7 +1,7 @@
 """Submodule for `ConditionConfig` configurable."""
 
 import re
-from ..configurable import configurable, Configurable, choice
+from ..configurable import configurable, Configurable, choice, required_choice
 
 @configurable(name='Additional address match conditions')
 class ConditionConfig(Configurable):
@@ -14,32 +14,16 @@ class ConditionConfig(Configurable):
 
     #pylint: disable=E0211,E0213,E0202
 
-    @choice
+    @required_choice
     def internal():
         """This key specifies the internal signal to use for the match
-        condition, if applicable. Either this key or `input` must be
-        specified."""
-        yield (None, 'no internal is specified, `input` must be specified '
-               'instead.')
+        condition."""
         yield (re.compile('[a-zA-Za-z][a-zA-Z0-9_]*'), 'a scalar internal '
                'with the given name is used for the match condition.')
         yield (re.compile('[a-zA-Za-z][a-zA-Z0-9_]*:[0-9]+'), 'a vector '
                'internal with the given name and width is used for the match '
                'condition.')
 
-    @choice
-    def input():
-        """This key specifies the external input signal to use for the match
-        condition, if applicable. Either this key or `internal` must be
-        specified."""
-        yield (None, 'no external input is specified, `internal` must be '
-               'specified instead.')
-        yield (re.compile('[a-zA-Za-z][a-zA-Z0-9_]*'), 'a scalar input signal '
-               'with the given name is used for the match condition.')
-        yield (re.compile('[a-zA-Za-z][a-zA-Z0-9_]*:[0-9]+'), 'a vector input '
-               'signal with the given name and width is used for the match '
-               'condition.')
-
     @choice
     def value():
         """This key specifies the value that the signal must have for the

vhdmmio/config/metadata.py

@@ -21,7 +21,10 @@ def mnemonic(self, value):
         descriptions. `vhdmmio` requires that they are unique within the
         current context only; that is, two fields in a single logical
         register cannot have the same mnemonic, but if they were in different
-        logical registers this would be fine.
+        logical registers this would be fine. However, chains of mnemonics
+        separated by underscores must still be unique. For instance, it's
+        illegal to have a register `X` containing field `Y_Z` and another
+        register `X_Y` containing field `Z`.
 
         If the mnemonic names an array, it cannot end in a number, since the
         array index is added to the mnemonic in various contexts.

vhdmmio/config/subaddress.py

@@ -11,8 +11,8 @@ class SubAddressConfig(Configurable):
     called a subaddress. This configuration structure specifies part of a
     custom subaddress format.
 
-    Note that exactly one of the `address`, `internal`, `input`, and `blank`
-    keys must be specified."""
+    Note that exactly one of the `address`, `internal`, and `blank` keys must
+    be specified."""
 
     #pylint: disable=E0211,E0213,E0202
 
@@ -41,20 +41,6 @@ def internal():
         yield (re.compile(r'[a-zA-Za-z][a-zA-Z0-9_]*:[0-9]+'), 'a vector '
                'internal with the given name and width is inserted into the '
                'subaddress at the current position.')
-
-    @choice
-    def input():
-        """This key specifies that this component of the subaddress is based
-        on the value of an external input signal."""
-        yield (None, 'this subaddress component is not based on an external '
-               'input signal.')
-        yield (re.compile(r'[a-zA-Za-z][a-zA-Z0-9_]*'), 'a scalar external '
-               'input signal with the given name is inserted into the '
-               'subaddress at the current position.')
-        yield (re.compile(r'[a-zA-Za-z][a-zA-Z0-9_]*:[0-9]+'), 'a vector '
-               'external input signal with the given name and width is '
-               'inserted into the subaddress at the current position.')
-
     @choice
     def blank():
         """This key specifies that a number of blank bits should be inserted as
@@ -67,10 +53,10 @@ def blank():
 
     @choice
     def slice():
-        """For component based on vector signals (`internal` and `input`), this
-        key allows you to use only a subset of the signal for this component.
-        In conjunction with other subaddress components based on the same
-        signal, this allows bits to be reordered."""
+        """For component based on vector internal signals, this key allows you
+        to use only a subset of the signal for this component. In conjunction
+        with other subaddress components based on the same signal, this allows
+        bits to be reordered."""
         yield None, 'the entire vector is used.'
         yield (0, None), 'only the specified bit within the vector is used.'
         yield ((re.compile(r'[0-9]+\.\.[0-9]+'), '`<high>..<low>`'),

vhdmmio/core/addressing.py

@@ -2,33 +2,22 @@
 paging."""
 
 from collections import namedtuple, OrderedDict
+from .shaped import Shaped
 
-class AddressSignal:
+class AddressSignal(Shaped):
     """Represents a signal that is mapped to one or more internal address
     bits. Intended to be subclassed based on the signal type, its origin, etc.
-    Needed by the base class are a name for documentation and an xwidth to
-    represent the signal's vectorness."""
+    Needed by the base class are a name for documentation and a shape."""
 
-    def __init__(self, name, xwidth=None):
-        super().__init__()
+    def __init__(self, name, shape=None):
+        super().__init__(shape=shape)
         self._name = name
-        self._xwidth = xwidth
 
     @property
     def name(self):
         """Name of the signal, mostly intended for the documentation output."""
         return self._name
 
-    @property
-    def xwidth(self):
-        """Width of the signal in bits for vectors, None for scalar signals."""
-        return self._xwidth
-
-    @property
-    def width(self):
-        """Width of the signal in bits regardless of vectorness."""
-        return self._xwidth if self._xwidth is not None else 1
-
     def __hash__(self):
         return id(self)
 
@@ -39,10 +28,10 @@ def __ne__(self, other):
         return self is not other
 
     def __str__(self):
-        return self._name
+        return self.name
 
     def __repr__(self):
-        return 'AddressSignal(%r, %r)' % (self._name, self._xwidth)
+        return 'AddressSignal(%r, %r)' % (self.name, self.shape)
 
     def doc_represent(self, value):
         """Represents an address matching operation for this signal against the