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Winch: implement rmw and, xor and or for x64 #10023

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merged 2 commits into from
Jan 19, 2025

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MarinPostma
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@MarinPostma MarinPostma commented Jan 15, 2025

Implement related atomic rmw for winch x64 backend:

  • and:
    • i32.atomic.rmw8.and_u
    • i32.atomic.rmw16.and_u
    • i32.atomic.rmw.and
    • i64.atomic.rmw8.and_u
    • i64.atomic.rmw16.and_u
    • i64.atomic.rmw32.and_u
    • i64.atomic.rmw.and
  • or:
    • i32.atomic.rmw8.or_u
    • i32.atomic.rmw16.or_u
    • i32.atomic.rmw.or
    • i64.atomic.rmw8.or_u
    • i64.atomic.rmw16.or_u
    • i64.atomic.rmw32.or_u
    • i64.atomic.rmw.or
  • xor:
    • i32.atomic.rmw8.xor_u
    • i32.atomic.rmw16.xor_u
    • i32.atomic.rmw.xor
    • i64.atomic.rmw8.xor_u
    • i64.atomic.rmw16.xor_u
    • i64.atomic.rmw32.xor_u
    • i64.atomic.rmw.xor

#9734

@MarinPostma MarinPostma marked this pull request as ready for review January 15, 2025 22:31
@MarinPostma MarinPostma requested review from a team as code owners January 15, 2025 22:31
@MarinPostma MarinPostma requested review from fitzgen and removed request for a team January 15, 2025 22:31
@github-actions github-actions bot added cranelift Issues related to the Cranelift code generator cranelift:area:x64 Issues related to x64 codegen winch Winch issues or pull requests labels Jan 15, 2025
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@saulecabrera saulecabrera requested review from saulecabrera and removed request for a team and fitzgen January 16, 2025 10:48
@MarinPostma MarinPostma changed the title Winch: implement rmw and, and or for x64 Winch: implement rmw and, xor and or for x64 Jan 16, 2025
@MarinPostma MarinPostma force-pushed the winch-x64-rmw-and branch 3 times, most recently from 3324880 to 3f8c463 Compare January 16, 2025 17:07
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Winch pieces look good to me, modulo the panic comment below.

Comment on lines +1343 to +1423
_ => unreachable!(
"invalid op for atomic_rmw_seq, should be one of `or`, `and` or `xor`"
),
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Could you return an error here instead of panicking?

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does it make sense to return an error here? we explicitely check that we only match the right variants above, this branch should be legitmately unreachable. No CodeGenError seem to correspond, so I was reluctant to add an error variant for a trivially unreachable statement.

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Yeah you're right, it's probably fine as is. I'm trying to error on the side of caution when it comes to panics, because we've put a lot of effort to make sure that they are minimal, particularly if they affect partial development of features at the visitor/masm layer. Here I got confused by the nested match which led me to think that we were missing an implementation.

@@ -30,6 +30,7 @@ use args::*;
// Instructions (top level): definition

// `Inst` is defined inside ISLE as `MInst`. We publicly re-export it here.
pub use super::lower::isle::generated_code::AtomicRmwSeqOp;
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I don't see an issue with exposing this. However, given that I'm not deeply familiar with the history of x64 backend in Cranelift, I'll kindly ask @cfallin for confirmation.

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@MarinPostma just a heads up that there are a couple of conflicts that need to be resolved before merging.

implement rmw or

implement atomic rmw xor

fix operand sizes

implement and, or, xor

update rmw or tests

update rmw xor tests

fmt

use ad-hoc conversion for AtomicRmwSeqOp

fix test

fix rebae quirks
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@saulecabrera I squashed to make conflict resolution more manageable

@saulecabrera saulecabrera added this pull request to the merge queue Jan 19, 2025
Merged via the queue into bytecodealliance:main with commit 2eb6513 Jan 19, 2025
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