feat CI: Add CI for stable version

.github/workflows/build.yml

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+on: [push, pull_request]
+name: build
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout source code
+        uses: actions/checkout@v2
+
+      - name: Install stable toolchain
+        uses: actions-rs/toolchain@v1
+        with:
+          toolchain: stable
+
+      - name: Build the application
+        uses: actions-rs/cargo@v1
+        with:
+          command: build
+
+      - name: Run tests
+        uses: actions-rs/cargo@v1
+        with:
+          command: test
+          args: --workspace
+
+      - name: Lint the code
+        uses: actions-rs/clippy-check@v1
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}
+
+      - name: Check if code formatted
+        uses: actions-rs/cargo@v1
+        with:
+          command: fmt
+          args: --all -- --check --verbose

.gitignore

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+target

Cargo.toml

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+[package]
+name = "do-core1"
+version = "0.1.0"
+authors = ["Samuel Ortiz <sameo@linux.intel.com>"]
+edition = "2018"
+
+[dependencies]
+clap = "2.33.3"
+do-core = { path = "do-core" }
+
+[workspace]
+members = [
+    "do-core"
+]

README.md

@@ -1,2 +1,53 @@
 # do-core1
-DO processor
+
+The `do-core1` is a simple processor architecture, mostly for educational purposes.
+
+It aims at being a support for system programming and computer architecture fundamentals courses.
+
+## Instruction Set Architecture
+
+The do-core1 [Instruction Set Architecture (ISA)](https://en.wikipedia.org/wiki/Instruction_set) is a simple [Reduced Instruction Set Computer (RISC)](https://en.wikipedia.org/wiki/Reduced_instruction_set_computer)
+processor architecture, with a very limited memory model and instruction and register set.
+
+### Registers
+
+`do-core1` exposes **8 general purpose registers**: `R0`, `R1`, `R2`, `R3`, `R4`, `R5`, `R6`, `R7`.
+
+It also uses one Instruction Pointer (`RIP`) register and a operation flags (`RFLAGS`) register.
+
+All `do-core1` registers are **16 bits wide**.
+
+### Memory Model
+
+`do-core1` can address up to **4KiB (4096 bytes) of physical memory**.
+
+### Instruction Set
+
+`do-core1` is a [RISC](https://en.wikipedia.org/wiki/Reduced_instruction_set_computer) architecture and executes fixed-length
+instructions of 16 bits.
+
+The `do-core1` is a 2-operand architecture, i.e. its instruction takes at most 2 operands.
+`do-core1` operands are register indexes.
+
+A `do-core1` instruction can be split into an operation code (opcode), the first operand (op0)
+and the second operand (op1). The opcode is 8 bits long, and both operands are 4 bits long:
+
+```
+do-core instruction (16 bits)
+
+Bits  |15                   8|7                4|3               0|
+      -------------------------------------------------------------
+      |  Opcode (bits 15-8)  |  op0 (bits 7-4)  | op1 (bits 3-0)  |
+      -------------------------------------------------------------
+```
+
+The `do-core1` is a [load-store](https://en.wikipedia.org/wiki/Load%E2%80%93store_architecture)
+architecture and supports the following instructions:
+
+
+| Opcode | Instruction  | Description                                                          |
+|--------|--------------|----------------------------------------------------------------------|
+| `0x00` | `LD Rn, Rm`  | Load the value at the memory address contained in `Rm` into `Rn`     |
+| `0x01` | `ST Rn, Rm`  | Store the value from `Rn` into the memory address contained in `Rm`  |
+| `0x02` | `ADD Rn, Rm` | Add the value contained in `Rm` into `Rn` (`Rn = Rn + Rm`)           |
+| `0x03` | `XOR Rn, Rm` | Perform a bitwise exclusive OR between `Rn` and `Rm`(`Rn = Rn ^ Rm`) |

do-core/Cargo.toml

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+[package]
+name = "do-core"
+version = "0.1.0"
+authors = ["Samuel Ortiz <sameo@linux.intel.com>"]
+edition = "2018"
+
+[dependencies]

do-core/src/core.rs

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+use crate::instruction::{Instruction, OpCode};
+use crate::memory::Memory;
+use crate::{Error, MAX_REGISTER_INDEX, MEMORY_SIZE};
+
+pub struct Core {
+    registers: [u16; MAX_REGISTER_INDEX as usize + 1],
+    memory: Memory,
+}
+
+impl Core {
+    pub fn new() -> Self {
+        let mut core = Core {
+            registers: [0u16; MAX_REGISTER_INDEX as usize + 1],
+            memory: Memory::new(MEMORY_SIZE),
+        };
+
+        // Arbitrary initial registers value.
+        // Registers will eventually be initialized through memory loads.
+        for (index, register) in core.registers.iter_mut().enumerate() {
+            *register = index as u16 * 0x10;
+        }
+
+        core
+    }
+
+    pub fn register(&self, index: u8) -> Result<u16, Error> {
+        if index > MAX_REGISTER_INDEX {
+            return Err(Error::Op0OutOfRange);
+        }
+
+        Ok(self.registers[index as usize])
+    }
+
+    pub fn dump(&self, preamble: &str) {
+        println!("do-core1: {}:", preamble);
+        for (index, register) in self.registers.iter().enumerate() {
+            println!("\tR{}: {:#x?}", index, *register);
+        }
+    }
+
+    pub fn decode(&mut self, insn: u16) -> Result<Instruction, Error> {
+        Instruction::disassemble(insn)
+    }
+
+    pub fn execute(&mut self, insn: Instruction) -> Result<(), Error> {
+        let opcode = insn.opcode();
+
+        match opcode {
+            OpCode::ADD => self.add(insn)?,
+            OpCode::XOR => self.xor(insn)?,
+            OpCode::LD => self.load(insn)?,
+            OpCode::ST => self.store(insn)?,
+        }
+
+        Ok(())
+    }
+
+    fn add(&mut self, insn: Instruction) -> Result<(), Error> {
+        let op0 = insn.op0() as usize;
+        let op1 = insn.op1() as usize;
+
+        self.registers[op0] =
+            self.registers[op0]
+                .checked_add(self.registers[op1])
+                .ok_or(Error::AdditionOverflow(
+                    self.registers[op0],
+                    self.registers[op1],
+                ))?;
+
+        Ok(())
+    }
+
+    fn xor(&mut self, insn: Instruction) -> Result<(), Error> {
+        let op0 = insn.op0() as usize;
+        let op1 = insn.op1() as usize;
+
+        self.registers[op0] ^= self.registers[op1];
+
+        Ok(())
+    }
+
+    fn load(&mut self, insn: Instruction) -> Result<(), Error> {
+        let op0 = insn.op0() as usize;
+        let op1 = insn.op1() as usize;
+
+        self.registers[op0] = self.memory.load(self.registers[op1])?.into();
+
+        Ok(())
+    }
+
+    fn store(&mut self, insn: Instruction) -> Result<(), Error> {
+        let op0 = insn.op0() as usize;
+        let op1 = insn.op1() as usize;
+
+        self.memory
+            .store(self.registers[op1], self.registers[op0] as u8)
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use crate::core::Core;
+    use crate::Error;
+
+    #[test]
+    fn test_core_add_r4_r5() -> Result<(), Error> {
+        let insn = 0x245;
+        let mut cpu = Core::new();
+
+        let r4 = cpu.register(4)?;
+        let r5 = cpu.register(5)?;
+
+        let decoded_insn = cpu.decode(insn)?;
+        cpu.execute(decoded_insn)?;
+
+        let new_r4 = cpu.register(4)?;
+
+        assert_eq!(new_r4, r4 + r5);
+
+        Ok(())
+    }
+
+    #[test]
+    fn test_core_xor_r1_r7() -> Result<(), Error> {
+        let insn = 0x317;
+        let mut cpu = Core::new();
+
+        let r1 = cpu.register(1)?;
+        let r7 = cpu.register(7)?;
+
+        let decoded_insn = cpu.decode(insn)?;
+        cpu.execute(decoded_insn)?;
+
+        let new_r1 = cpu.register(1)?;
+
+        assert_eq!(new_r1, r1 ^ r7);
+
+        Ok(())
+    }
+}