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feat CI: Add CI for stable version #10

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wants to merge 45 commits into from
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feat CI: Add CI for stable version #10

wants to merge 45 commits into from

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thomasgouveia
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This PR contains the necessary to run a simple CI job on our project.

Actually the CI is configured to build the application with the stable toolchain, run all tests, run cargo clippy and cargo fmt.

Missing behaviors:

  • Build the app with the nightly release
  • Build the app with the beta release

Samuel Ortiz added 30 commits February 6, 2021 14:12
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
It always starts from here.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Define 2 variables on the stack and add them together.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
do-core1 registers are 16 bits wide.
Use Rust static typing to enforce that.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce mutability by adding the addition result to the first operand.
The first operand must be defined as mutable, or else we fail to build.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce the function syntax to abstract registers addition.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce Rust flow control (i.e. if) in order to check that we add only
when the opcode is ADD. Panic! otherwise.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce Rust's versatile Enum for defining a new type: OpCode.
First pattern matching code path.
Pretty print the Enum value.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce compiler linting and actually turn it off for non supported
opcodes.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Live exercice #1.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce Rust print formatting rules.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
The disassembler takes a fixed 16 bits instruction and tries to decode
it into an opcode, and 2 operands.

This intentionnaly fails to build, as it needs OpCode::from_u8.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce the impl Rust keyword, for type implementations.
Here it's an Enum.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
The Instruction constructor is a disassembler, it can not be overloaded
with other constructors.

Live exercice #2.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce Rust's unit testing framework.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
We add more tests for disassembling all supported instructions.

Live exercice #3.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce external crates dependencies through the clap crate.
Rust's std library is scarce and limited, no command line parsing for
example.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Add partial error handling for the instruction disassembler.
Introduce the Result type and do basic and naive error handling (panic!
if disassemble() returns an error).

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce Rust error pattern matching.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
With naive pattern matching check.

Live exercice #4.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Simple example showing how the ? operator replaces the previous naive
patter matching.
Show how errors can be forwarded all the way up to main.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Introduce the Option type.
Show how to convert an Option to a Result and carry errors forward.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
All broken after adding the error handling code.

Live exercice #5.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Now that we know if disassembling reported an error or not, we can
implement negative unit testing.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
In order to manipulate more than R0 and R1, we define a static array of
8 u16 values.
Introduce Rust collection (A simple array).

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Now that we have a complete set of registers, it is more convenient to
be able to print all of them.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This is temporary. Eventually, there will be a Cpu constructor, and
potentially register initialization through memory loads.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
With a minimal content, just our opcodes.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Samuel Ortiz and others added 15 commits March 7, 2021 23:46
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
And define a workspace.

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Related issue: #3
This is for do-core-asm to be able to depend on us for its opcodes needs

Signed-off-by: Eliott Veyrier <eliott.veyrier@umontpellier.fr>
Signed-off-by: Eliott Veyrier <eliott.veyrier@umontpellier.fr>
@thomasgouveia thomasgouveia mentioned this pull request Mar 23, 2021
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@thomasgouveia Thanks a lot for the PR.

Could we please reorganize the commits in order to only have 3 of them:

  1. The basic github action (with all 3 toolchains)
  2. The cargo fmt addition
  3. The cargo clippy one with the actual code fixes

@thomasgouveia thomasgouveia closed this by deleting the head repository Oct 22, 2022
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2 participants