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Verilog: fix for named generate block scopes #1150

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Verilog: fix for named generate block scopes #1150

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Verilog generate blocks may be named, which creates a scope.

@kroening kroening marked this pull request as ready for review June 10, 2025 16:28
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Verilog: fix for named generate block scopes
4f35181 
Verilog generate blocks may be named, which creates a scope.
@kroening kroening force-pushed the generate-block-scope branch from e35c701 to 4f35181 Compare June 10, 2025 16:29
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