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Synthesis

Add Verilog Module Synthesis Workflow #1

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Add Verilog Module Synthesis Workflow

Add Verilog Module Synthesis Workflow #1

Triggered via pull request February 5, 2025 21:16
@ewdlopewdlop
opened #22
add-synthesis-workflow
Status Failure
Total duration 33s
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synthesis.yml

on: pull_request
synthesize
23s
synthesize
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synthesize
Process completed with exit code 1.