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CodeQL #6: by ewdlop
February 15, 2025 00:47 1m 2s main
February 15, 2025 00:47 1m 2s
Merge pull request #25 from ewdlop/ewdlop-patch-23
Synthesize Verilog Modules #8: Commit 65cbe28 pushed by ewdlop
February 15, 2025 00:47 8m 45s main
February 15, 2025 00:47 8m 45s
PR #25
CodeQL #5: by ewdlop
February 15, 2025 00:47 1m 14s refs/pull/25/head
February 15, 2025 00:47 1m 14s
Create bcd_digital_clock.v
Synthesize Verilog Modules #7: Pull request #25 opened by ewdlop
February 15, 2025 00:47 8m 31s ewdlop-patch-23
February 15, 2025 00:47 8m 31s
Push on main
CodeQL #4: by ewdlop
February 15, 2025 00:35 1m 11s main
February 15, 2025 00:35 1m 11s
Merge pull request #24 from ewdlop/ewdlop-patch-22
Synthesize Verilog Modules #6: Commit 860f561 pushed by ewdlop
February 15, 2025 00:35 8m 26s main
February 15, 2025 00:35 8m 26s
Create README.md
Synthesize Verilog Modules #5: Pull request #24 opened by ewdlop
February 15, 2025 00:35 9m 15s ewdlop-patch-22
February 15, 2025 00:35 9m 15s
PR #24
CodeQL #3: by ewdlop
February 15, 2025 00:35 1m 6s refs/pull/24/head
February 15, 2025 00:35 1m 6s
Scheduled
CodeQL #2: by github-advanced-security bot
February 10, 2025 08:20 1m 12s main
February 10, 2025 08:20 1m 12s
CodeQL Setup
CodeQL #1: by ewdlop
February 5, 2025 21:18 1m 13s main
February 5, 2025 21:18 1m 13s
Merge pull request #23 from ewdlop/ewdlop-patch-21
Synthesize Verilog Modules #4: Commit 0e8b60c pushed by ewdlop
February 5, 2025 21:18 8m 25s main
February 5, 2025 21:18 8m 25s
Update synthesis.yml
Synthesize Verilog Modules #3: Pull request #23 opened by ewdlop
February 5, 2025 21:18 8m 30s ewdlop-patch-21
February 5, 2025 21:18 8m 30s
Merge pull request #22 from ewdlop/add-synthesis-workflow
Synthesize Verilog Modules #2: Commit 265a720 pushed by ewdlop
February 5, 2025 21:16 28s main
February 5, 2025 21:16 28s
Add Verilog Module Synthesis Workflow
Synthesize Verilog Modules #1: Pull request #22 opened by ewdlop
February 5, 2025 21:16 33s add-synthesis-workflow
February 5, 2025 21:16 33s