Merge pull request #25 from ewdlop/ewdlop-patch-23 #8

# to view logs

	name: Synthesize Verilog Modules

	on:
	push:
	branches:
	- main # You can specify your main branch or all branches
	pull_request:
	branches:
	- main # Runs for pull requests targeting the main branch

	jobs:
	synthesize:
	runs-on: ubuntu-latest # The environment to run the job on

	steps:
	# Step 1: Check out the repository
	- name: Checkout repository
	uses: actions/checkout@v2

	# Step 2: Set up Yosys synthesis tool
	- name: Install Yosys
	run: \|
	sudo apt update
	sudo apt install -y build-essential clang bison flex libreadline-dev \
	git gawk tcl zlib1g-dev
	git clone --recursive https://github.com/YosysHQ/yosys
	cd yosys
	make
	sudo make install

	# Step 3: Run Yosys on Verilog files to check for synthesis errors
	- name: Run Yosys Synthesis
	run: \|
	yosys -p "read_verilog $(find . -name '*.v'); synth -top top_module" > synthesis_log.txt
	cat synthesis_log.txt

	# Step 4: Check if synthesis was successful
	- name: Check synthesis log for errors
	run: \|
	if grep -q "error" synthesis_log.txt; then
	echo "Synthesis failed. Check synthesis_log.txt for errors."
	exit 1
	else
	echo "Synthesis successful!"
	fi

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