Sync with SPIR-V Translator de0957d85bcaa

llvm-spirv/lib/SPIRV/OCLUtil.h

@@ -165,6 +165,7 @@ const static char Dot[] = "dot";
 const static char EnqueueKernel[] = "enqueue_kernel";
 const static char FMax[] = "fmax";
 const static char FMin[] = "fmin";
+const static char FPGARegIntel[] = "__builtin_intel_fpga_reg";
 const static char GetFence[] = "get_fence";
 const static char GetImageArraySize[] = "get_image_array_size";
 const static char GetImageChannelOrder[] = "get_image_channel_order";

llvm-spirv/lib/SPIRV/SPIRVReader.cpp

@@ -1756,6 +1756,52 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F,
   case OpGetKernelNDrangeSubGroupCount:
     return mapValue(
         BV, transSGSizeQueryBI(static_cast<SPIRVInstruction *>(BV), BB));
+  case OpFPGARegINTEL: {
+    IRBuilder<> Builder(BB);
+
+    SPIRVFPGARegINTELInstBase *BC =
+        static_cast<SPIRVFPGARegINTELInstBase *>(BV);
+
+    PointerType *Int8PtrTyPrivate =
+        Type::getInt8PtrTy(*Context, SPIRAS_Private);
+    IntegerType *Int32Ty = Type::getInt32Ty(*Context);
+
+    Value *UndefInt8Ptr = UndefValue::get(Int8PtrTyPrivate);
+    Value *UndefInt32 = UndefValue::get(Int32Ty);
+
+    Constant *GS = Builder.CreateGlobalStringPtr(kOCLBuiltinName::FPGARegIntel);
+
+    Type *Ty = transType(BC->getType());
+    Value *Val = transValue(BC->getOperand(0), F, BB);
+
+    Value *ValAsArg = Val;
+    Type *RetTy = Ty;
+    auto IID = Intrinsic::annotation;
+    if (!isa<IntegerType>(Ty)) {
+      // All scalar types can be bitcasted to a same-sized integer
+      if (!isa<PointerType>(Ty) && !isa<StructType>(Ty)) {
+        RetTy = IntegerType::get(*Context, Ty->getPrimitiveSizeInBits());
+        ValAsArg = Builder.CreateBitCast(Val, RetTy);
+      }
+      // If pointer type or struct type
+      else {
+        IID = Intrinsic::ptr_annotation;
+        auto *PtrTy = dyn_cast<PointerType>(Ty);
+        if (PtrTy && isa<IntegerType>(PtrTy->getElementType()))
+          RetTy = PtrTy;
+        // Whether a struct or a pointer to some other type,
+        // bitcast to i8*
+        else {
+          RetTy = Int8PtrTyPrivate;
+          ValAsArg = Builder.CreateBitCast(Val, Int8PtrTyPrivate);
+        }
+      }
+    }
+
+    Value *Args[] = {ValAsArg, GS, UndefInt8Ptr, UndefInt32};
+    auto *IntrinsicCall = Builder.CreateIntrinsic(IID, RetTy, Args);
+    return mapValue(BV, IntrinsicCall);
+  }
   default: {
     auto OC = BV->getOpCode();
     if (isSPIRVCmpInstTransToLLVMInst(static_cast<SPIRVInstruction *>(BV))) {

llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

@@ -87,7 +87,7 @@ using namespace OCLUtil;
 
 namespace SPIRV {
 
-cl::opt<bool> SPIRVMemToReg("spirv-mem2reg", cl::init(true),
+cl::opt<bool> SPIRVMemToReg("spirv-mem2reg", cl::init(false),
                             cl::desc("LLVM/SPIR-V translation enable mem2reg"));
 
 cl::opt<bool> SPIRVNoDerefAttr(
@@ -258,7 +258,7 @@ SPIRVType *LLVMToSPIRV::transType(Type *T) {
     return mapType(T, BM->addFloatType(T->getPrimitiveSizeInBits()));
 
   // A pointer to image or pipe type in LLVM is translated to a SPIRV
-  // sampler or pipe type.
+  // (non-pointer) image or pipe type.
   if (T->isPointerTy()) {
     auto ET = T->getPointerElementType();
     assert(!ET->isFunctionTy() && "Function pointer type is not allowed");
@@ -1322,6 +1322,22 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
     return DbgTran->createDebugDeclarePlaceholder(cast<DbgDeclareInst>(II), BB);
   case Intrinsic::dbg_value:
     return DbgTran->createDebugValuePlaceholder(cast<DbgValueInst>(II), BB);
+  case Intrinsic::annotation: {
+    SPIRVType *Ty = transType(II->getType());
+
+    GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(II->getArgOperand(1));
+    if (!GEP)
+      return nullptr;
+    Constant *C = cast<Constant>(GEP->getOperand(0));
+    // TODO: Refactor to use getConstantStringInfo()
+    StringRef AnnotationString =
+        cast<ConstantDataArray>(C->getOperand(0))->getAsCString();
+
+    if (AnnotationString == kOCLBuiltinName::FPGARegIntel)
+      return BM->addFPGARegINTELInst(Ty, transValue(II->getOperand(0), BB), BB);
+
+    return nullptr;
+  }
   case Intrinsic::var_annotation: {
     SPIRVValue *SV;
     if (auto *BI = dyn_cast<BitCastInst>(II->getArgOperand(0))) {
@@ -1332,6 +1348,7 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
 
     GetElementPtrInst *GEP = cast<GetElementPtrInst>(II->getArgOperand(1));
     Constant *C = cast<Constant>(GEP->getOperand(0));
+    // TODO: Refactor to use getConstantStringInfo()
     StringRef AnnotationString =
         cast<ConstantDataArray>(C->getOperand(0))->getAsString();
 
@@ -1352,28 +1369,34 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
     } else {
       GI = dyn_cast<GetElementPtrInst>(II->getOperand(0));
     }
-    SPIRVType *Ty = transType(GI->getSourceElementType());
-
-    SPIRVWord MemberNumber =
-        dyn_cast<ConstantInt>(GI->getOperand(2))->getZExtValue();
 
     GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(II->getArgOperand(1));
     Constant *C = dyn_cast<Constant>(GEP->getOperand(0));
+    // TODO: Refactor to use getConstantStringInfo()
     StringRef AnnotationString =
-        dyn_cast<ConstantDataArray>(C->getOperand(0))->getAsString();
+        dyn_cast<ConstantDataArray>(C->getOperand(0))->getAsCString();
 
-    std::vector<std::pair<Decoration, std::string>> Decorations =
-        parseAnnotations(AnnotationString);
+    if (GI) {
+      auto *Ty = transType(GI->getSourceElementType());
+      SPIRVWord MemberNumber =
+          dyn_cast<ConstantInt>(GI->getOperand(2))->getZExtValue();
 
-    if (Decorations.empty()) {
-      Ty->addMemberDecorate(new SPIRVMemberDecorateUserSemanticAttr(
-          Ty, MemberNumber,
-          AnnotationString.substr(0, AnnotationString.size() - 1)));
+      std::vector<std::pair<Decoration, std::string>> Decorations =
+          parseAnnotations(AnnotationString);
+
+      if (Decorations.empty()) {
+        Ty->addMemberDecorate(new SPIRVMemberDecorateUserSemanticAttr(
+            Ty, MemberNumber, AnnotationString));
+      } else {
+        addIntelFPGADecorationsForStructMember(Ty, MemberNumber, Decorations);
+      }
+      II->replaceAllUsesWith(II->getOperand(0));
     } else {
-      addIntelFPGADecorationsForStructMember(Ty, MemberNumber, Decorations);
+      auto *Ty = transType(II->getType());
+      auto *BI = dyn_cast<BitCastInst>(II->getOperand(0));
+      if (AnnotationString == kOCLBuiltinName::FPGARegIntel)
+        return BM->addFPGARegINTELInst(Ty, transValue(BI, BB), BB);
     }
-
-    II->replaceAllUsesWith(II->getOperand(0));
     return 0;
   }
   default:

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h

@@ -117,7 +117,8 @@ enum SPIRVExtensionKind {
   SPV_INTEL_blocking_pipes,
   SPV_INTEL_device_side_avc_motion_estimation,
   SPV_KHR_no_integer_wrap_decoration,
-  SPV_INTEL_fpga_memory_attributes
+  SPV_INTEL_fpga_memory_attributes,
+  SPV_INTEL_fpga_reg
 };
 
 typedef std::set<SPIRVExtensionKind> SPIRVExtSet;
@@ -128,6 +129,7 @@ template <> inline void SPIRVMap<SPIRVExtensionKind, std::string>::init() {
       "SPV_INTEL_device_side_avc_motion_estimation");
   add(SPV_KHR_no_integer_wrap_decoration, "SPV_KHR_no_integer_wrap_decoration");
   add(SPV_INTEL_fpga_memory_attributes, "SPV_INTEL_fpga_memory_attributes");
+  add(SPV_INTEL_fpga_reg, "SPV_INTEL_fpga_reg");
 }
 
 template <> inline void SPIRVMap<SPIRVExtInstSetKind, std::string>::init() {

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h

@@ -873,6 +873,29 @@ class SPIRVPhi : public SPIRVInstruction {
   std::vector<SPIRVId> Pairs;
 };
 
+class SPIRVFPGARegINTELInstBase : public SPIRVInstTemplateBase {
+public:
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityFPGARegINTEL);
+  }
+
+  SPIRVExtSet getRequiredExtensions() const override {
+    return getSet(SPV_INTEL_fpga_reg);
+  }
+
+protected:
+  void validate() const override {
+    SPIRVInstruction::validate();
+
+    assert(OpCode == OpFPGARegINTEL &&
+           "Invalid op code for FPGARegINTEL instruction");
+    assert(getType() == getValueType(Ops[0]) && "Inconsistent type");
+  }
+};
+
+typedef SPIRVInstTemplate<SPIRVFPGARegINTELInstBase, OpFPGARegINTEL, true, 4>
+    SPIRVFPGARegINTEL;
+
 class SPIRVCompare : public SPIRVInstTemplateBase {
 protected:
   void validate() const override {

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h

@@ -1002,6 +1002,7 @@ inline bool isValid(spv::Op V) {
   case OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL:
   case OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL:
   case OpSubgroupAvcSicGetInterRawSadsINTEL:
+  case OpFPGARegINTEL:
     return true;
   default:
     return false;

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp

@@ -363,6 +363,8 @@ class SPIRVModuleImpl : public SPIRVModule {
   SPIRVInstruction *addVectorInsertDynamicInst(SPIRVValue *, SPIRVValue *,
                                                SPIRVValue *,
                                                SPIRVBasicBlock *) override;
+  SPIRVInstruction *addFPGARegINTELInst(SPIRVType *, SPIRVValue *,
+                                        SPIRVBasicBlock *) override;
 
   virtual SPIRVId getExtInstSetId(SPIRVExtInstSetKind Kind) const override;
 
@@ -1290,6 +1292,15 @@ SPIRVInstruction *SPIRVModuleImpl::addCopyMemorySizedInst(
                         BB);
 }
 
+SPIRVInstruction *SPIRVModuleImpl::addFPGARegINTELInst(SPIRVType *Type,
+                                                       SPIRVValue *V,
+                                                       SPIRVBasicBlock *BB) {
+  return addInstruction(
+      SPIRVInstTemplateBase::create(OpFPGARegINTEL, Type, getId(),
+                                    getVec(V->getId()), BB, this),
+      BB);
+}
+
 SPIRVInstruction *SPIRVModuleImpl::addVariable(
     SPIRVType *Type, bool IsConstant, SPIRVLinkageTypeKind LinkageType,
     SPIRVValue *Initializer, const std::string &Name,

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h

@@ -375,6 +375,8 @@ class SPIRVModule {
                                                        SPIRVValue *,
                                                        SPIRVValue *,
                                                        SPIRVBasicBlock *) = 0;
+  virtual SPIRVInstruction *addFPGARegINTELInst(SPIRVType *, SPIRVValue *,
+                                                SPIRVBasicBlock *) = 0;
   virtual SPIRVId getExtInstSetId(SPIRVExtInstSetKind Kind) const = 0;
 
   // I/O functions

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

@@ -490,6 +490,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
   add(CapabilityFPGAMemoryAttributesINTEL, "FPGAMemoryAttributesINTEL");
   add(CapabilityFPGALoopControlsINTEL, "FPGALoopControlsINTEL");
   add(CapabilityBlockingPipesINTEL, "BlockingPipesINTEL");
+  add(CapabilityFPGARegINTEL, "FPGARegINTEL");
 }
 SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
 

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h

@@ -431,3 +431,4 @@ _SPIRV_OP(SubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL, 5815)
 _SPIRV_OP(SubgroupAvcSicGetInterRawSadsINTEL, 5816)
 _SPIRV_OP(ReadPipeBlockingINTEL, 5946)
 _SPIRV_OP(WritePipeBlockingINTEL, 5947)
+_SPIRV_OP(FPGARegINTEL, 5949)

llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp

@@ -681,6 +681,7 @@ enum Capability {
   CapabilityFPGAMemoryAttributesINTEL = 5824,
   CapabilityFPGALoopControlsINTEL = 5888,
   CapabilityBlockingPipesINTEL = 5945,
+  CapabilityFPGARegINTEL = 5948,
   CapabilityMax = 0x7fffffff,
 };
 
@@ -1127,6 +1128,7 @@ enum Op {
   OpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
   OpReadPipeBlockingINTEL = 5946,
   OpWritePipeBlockingINTEL = 5947,
+  OpFPGARegINTEL = 5949,
   OpMax = 0x7fffffff,
 };
 

llvm-spirv/test/AtomicCompareExchange_cl20.ll

@@ -11,9 +11,6 @@ target triple = "spir-unknown-unknown"
 ; Int64Atomics capability must be declared only if atomic builtins have 64-bit integers arguments.
 ; CHECK-NOT: Capability Int64Atomics
 
-; CHECK: Name [[Pointer:[0-9]+]] "object"
-; CHECK: Name [[ComparatorPtr:[0-9]+]] "expected"
-; CHECK: Name [[Value:[0-9]+]] "desired"
 ; CHECK: 4 TypeInt [[int:[0-9]+]] 32 0
 ; CHECK: Constant [[int]] [[DeviceScope:[0-9]+]] 1
 ; CHECK: Constant [[int]] [[SequentiallyConsistent_MS:[0-9]+]] 16
@@ -22,9 +19,9 @@ target triple = "spir-unknown-unknown"
 
 ; Function Attrs: nounwind
 define spir_func void @test(i32 addrspace(4)* %object, i32 addrspace(4)* %expected, i32 %desired) #0 {
-; CHECK: FunctionParameter [[int_ptr]] [[Pointer]]
-; CHECK: FunctionParameter [[int_ptr]] [[ComparatorPtr]]
-; CHECK: FunctionParameter [[int]] [[Value]]
+; CHECK: FunctionParameter [[int_ptr]] [[object:[0-9]+]]
+; CHECK: FunctionParameter [[int_ptr]] [[expected:[0-9]+]]
+; CHECK: FunctionParameter [[int]] [[desired:[0-9]+]]
 
 entry:
   %object.addr = alloca i32 addrspace(4)*, align 4
@@ -39,11 +36,16 @@ entry:
   %0 = load i32 addrspace(4)*, i32 addrspace(4)** %object.addr, align 4
   %1 = load i32 addrspace(4)*, i32 addrspace(4)** %expected.addr, align 4
   %2 = load i32, i32* %desired.addr, align 4
-
-  %call = call spir_func zeroext i1 @_Z30atomic_compare_exchange_strongPVU3AS4U7_AtomiciPU3AS4ii(i32 addrspace(4)* %0, i32 addrspace(4)* %1, i32 %2)
-; CHECK: Load [[int]] [[Comparator:[0-9]+]] [[ComparatorPtr]]
+; CHECK: Store [[object_addr:[0-9]+]] [[object]]
+; CHECK: Store [[expected_addr:[0-9]+]] [[expected]]
+; CHECK: Store [[desired_addr:[0-9]+]] [[desired]]
+; CHECK: Load [[int_ptr]] [[Pointer:[0-9]+]] [[object_addr]]
+; CHECK: Load [[int_ptr]] [[exp:[0-9]+]] [[expected_addr]]
+; CHECK: Load [[int]] [[Value:[0-9]+]] [[desired_addr]]
+; CHECK: Load [[int]] [[Comparator:[0-9]+]] [[exp]]
 ; CHECK-NEXT: 9 AtomicCompareExchange [[int]] [[Result:[0-9]+]] [[Pointer]] [[DeviceScope]] [[SequentiallyConsistent_MS]] [[SequentiallyConsistent_MS]] [[Value]] [[Comparator]]
-; CHECK-NEXT: Store [[ComparatorPtr]] [[Result]]
+  %call = call spir_func zeroext i1 @_Z30atomic_compare_exchange_strongPVU3AS4U7_AtomiciPU3AS4ii(i32 addrspace(4)* %0, i32 addrspace(4)* %1, i32 %2)
+; CHECK-NEXT: Store [[exp]] [[Result]]
 ; CHECK-NEXT: IEqual [[bool]] [[CallRes:[0-9]+]] [[Result]] [[Comparator]]
 ; CHECK-NOT: [[Result]]
   %frombool = zext i1 %call to i8
@@ -57,10 +59,13 @@ entry:
   %5 = load i32 addrspace(4)*, i32 addrspace(4)** %expected.addr, align 4
   %6 = load i32, i32* %desired.addr, align 4
 
+; CHECK: Load [[int_ptr]] [[Pointer:[0-9]+]] [[object_addr]]
+; CHECK: Load [[int_ptr]] [[exp:[0-9]+]] [[expected_addr]]
+; CHECK: Load [[int]] [[Value:[0-9]+]] [[desired_addr]]
+; CHECK: Load [[int]] [[ComparatorWeak:[0-9]+]] [[exp]]
   %call2 = call spir_func zeroext i1 @_Z28atomic_compare_exchange_weakPVU3AS4U7_AtomiciPU3AS4ii(i32 addrspace(4)* %4, i32 addrspace(4)* %5, i32 %6)
-; CHECK: Load [[int]] [[ComparatorWeak:[0-9]+]] [[ComparatorPtr]]
 ; CHECK-NEXT: 9 AtomicCompareExchangeWeak [[int]] [[Result:[0-9]+]] [[Pointer]] [[DeviceScope]] [[SequentiallyConsistent_MS]] [[SequentiallyConsistent_MS]] [[Value]] [[ComparatorWeak]]
-; CHECK-NEXT: Store [[ComparatorPtr]] [[Result]]
+; CHECK-NEXT: Store [[exp]] [[Result]]
 ; CHECK-NEXT: IEqual [[bool]] [[CallRes:[0-9]+]] [[Result]] [[ComparatorWeak]]
 ; CHECK-NOT: [[Result]]
 

llvm-spirv/test/DebugInfo/BuiltinCallLocation.cl

@@ -8,7 +8,7 @@
 // CHECK-SPIRV: Label
 // CHECK-SPIRV: ExtInst {{.*}} DebugScope
 // CHECK-SPIRV: ExtInst {{.*}} sin
-// CHECK-LLVM: call spir_func float @_Z3sinf(float %x) {{.*}} !dbg ![[loc:[0-9]+]]
+// CHECK-LLVM: call spir_func float @_Z3sinf(float %{{.*}}) {{.*}} !dbg ![[loc:[0-9]+]]
 // CHECK-LLVM: ![[loc]] = !DILocation(line: 14, column: 10, scope: !{{.*}})
 float f(float x) {
   return sin(x);

llvm-spirv/test/DebugInfo/DebugDeclareUnused.cl

@@ -1,7 +1,7 @@
 // Check that we can translate llvm.dbg.declare for a local variable which was
-// deleted by mem2reg pass(enabled by default in llvm-spirv)
+// deleted by mem2reg pass(disabled by default in llvm-spirv)
 
-// RUN: %clang_cc1 %s -triple spir -disable-llvm-passes -debug-info-kind=standalone -emit-llvm-bc -o - | llvm-spirv -o %t.spv
+// RUN: %clang_cc1 %s -triple spir -disable-llvm-passes -debug-info-kind=standalone -emit-llvm-bc -o - | llvm-spirv -spirv-mem2reg -o %t.spv
 // RUN: llvm-spirv %t.spv -to-text -o - | FileCheck %s --check-prefix=CHECK-SPIRV
 // RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM