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21 Open 8 Closed
21 Open 8 Closed
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Issues list

Enable Modules to be run in SystemVerilog simulators enhancement New feature or request
#44 opened Jan 23, 2025 by mkorbel1
Add support for Cosim mixin on any Module instead of just ExternalSystemVerilogModule enhancement New feature or request
#43 opened Jan 23, 2025 by mkorbel1
Flaky test: "port test dart fail async" bug Something isn't working
#41 opened Jan 2, 2025 by mkorbel1
Add support for Verilator enhancement New feature or request
#40 opened Jan 2, 2025 by mkorbel1
1
Add support for in/out ports enhancement New feature or request
#39 opened Jan 2, 2025 by mkorbel1
Add testing for async reset (and async triggers in general) enhancement New feature or request
#38 opened Jan 2, 2025 by mkorbel1
Add ability to configure build and sim arguments at connection time enhancement New feature or request
#26 opened Feb 28, 2023 by mkorbel1
Resolve race condition in RohdConnector during interactive debug and SV timeout bug Something isn't working
#15 opened Feb 8, 2023 by mkorbel1
Add indication in RohdConnector when a failure was encountered
#14 opened Feb 8, 2023 by mkorbel1
Add testing that SV # delays are properly handled enhancement New feature or request
#13 opened Feb 8, 2023 by mkorbel1
Add more extensive testing that throwOnUnexpectedEnd works with PortConfig enhancement New feature or request
#12 opened Feb 8, 2023 by mkorbel1
Add a PortConfig test where the process crashes before Simulator.run enhancement New feature or request good first issue Good for newcomers
#11 opened Feb 8, 2023 by mkorbel1
Add testing for 0-width input and output ports
#9 opened Feb 8, 2023 by mkorbel1
Don't send more ticks than necessary enhancement New feature or request
#8 opened Feb 8, 2023 by mkorbel1
Add a test covering scenarios with multiple SV simulator ticks per timestamp enhancement New feature or request
#7 opened Feb 8, 2023 by mkorbel1
Add testing for clock-divider logic with cosimulation enhancement New feature or request
#6 opened Feb 7, 2023 by mkorbel1
Listeners linger after simulations end bug Something isn't working
#5 opened Feb 7, 2023 by mkorbel1
Add more types of arguments for Cosim Modules enhancement New feature or request
#4 opened Feb 7, 2023 by mkorbel1
Build an annotation-based cosim-wrapper code generator enhancement New feature or request
#3 opened Feb 7, 2023 by mkorbel1
Enable cosim access to hierarchically reference signals in SystemVerilog modules and submodules enhancement New feature or request
#2 opened Feb 7, 2023 by mkorbel1
Use typing for cosim messages enhancement New feature or request
#1 opened Feb 7, 2023 by mkorbel1
ProTip! Find all open issues with in progress development work with linked:pr.