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Support for LogicArray ports #34

Merged
merged 2 commits into from
Nov 29, 2023
Merged

Support for LogicArray ports #34

merged 2 commits into from
Nov 29, 2023

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mkorbel1
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Description & Motivation

ROHD v0.5.0 supports LogicArrays, including as ports, and for both packed and unpacked dimensions. This PR adds support (and testing) for cosimulating with a SystemVerilog module which has arrays (unpacked and packed, multidimensional) with the rohd-cosim package.

Related Issue(s)

Fix #32

Testing

Added new tests for packed only, 1D unpacked, and 2D unpacked.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

@mkorbel1 mkorbel1 merged commit cb7832f into intel:main Nov 29, 2023
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@mkorbel1 mkorbel1 deleted the arrays branch November 29, 2023 20:23
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Support LogicArray ports
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