rustc_target: RISC-V: add base `I`-related important extensions #138823

a4lg · 2025-03-22T04:48:06Z

Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria:

Formerly a part of the I extension and splitted thereafter (now ratified as I + Zifencei + Zicsr + Zicntr + Zihpm) or
Dicoverable from newer versions of the Linux kernel and implemented as a part of std_detect's feature (Zihintpause) and
Available on LLVM 18.

This is based on the latest ratified ISA Manuals (version 20240411).

LLVM Definitions:

Additional (1):
One of those, Zicsr, is a dependency of many other ISA extensions and this commit adds correct dependencies to Zicsr.

Additional (2):
In RISC-V, G is an abbreviation of following extensions:

I
M
A
F
D
Zicsr (although implied by F)
Zifencei

and all RISC-V targets with the G abbreviation and targets for Android / VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC. For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates riscv32-wrs-vxworks though).

This is the version 4.
Ztso in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental Ztso requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding Ztso is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry Zihintpause).

Version 4:

Fixed some commit messages,
Added Android / VxWorks targets to imply G and
Added an implication from Zve32x to Zicsr (which makes all vector extension subsets to imply Zicsr)
since rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742 is now merged.

Tracking issue for RFC 2045: improving #[target_feature] #44839
(riscv_target_feature)
Tracking Issue for RISC-V Ratified Extensions Intrinsics #114544
(This PR can be a prerequisite of resolving a part of that tracking issue)
rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742
(Touches the same place and vector extensions depend on Zicsr)

NOT Related but linked:

Some -Ctarget-features must be restrained on RISCV #132618
(This PR won't be blocked by this issue since none of those extensions do not change the ABI)

@rustbot r? @Amanieu
@rustbot label +T-compiler +O-riscv +A-target-feature

rustbot · 2025-03-24T02:31:01Z

These commits modify compiler targets.
(See the Target Tier Policy.)

taiki-e · 2025-03-25T17:11:11Z

and all targets with either "riscv32gc" or "riscv64gc" are updated accordingly.

I think the following two that do not include extension names in the target name are also actually riscv64gc.

rust/compiler/rustc_target/src/spec/targets/riscv64_linux_android.rs

Line 22 in 48994b1

features: "+m,+a,+f,+d,+c,+zba,+zbb,+zbs,+v".into(),

rust/compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs

Line 19 in 48994b1

features: "+m,+a,+f,+d,+c".into(),

Amanieu · 2025-03-28T10:07:54Z

@a4lg Could you update the 2 targets mentioned by @taiki-e. Then this should be good to merge.

a4lg · 2025-04-01T13:03:36Z

@taiki-e I wasn't sure whether this is okay as RV64G.
@Amanieu Okay, I'll update that, too.

a4lg · 2025-04-01T14:37:03Z

Confirmed.
Android will require RVA22 + vector + vector crypto extensions (I could not confirm which vector crypto extensions), which is a superset of RV(32|64)GCV.
I could not confirm minimum requirements of VxWorks but at least all BSPs currently supplied by Wind River are for boards with RV64GC (archive).

Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria: * Formerly a part of the "I" extension and splitted thereafter (now ratified as "I" + "Zifencei" + "Zicsr" + "Zicntr" + "Zihpm") or * Dicoverable from newer versions of the Linux kernel and implemented as a part of std_detect's feature ("Zihintpause"). This is based on the latest ratified ISA Manuals (version 20240411). Additional (1): One of those, "Zicsr", is a dependency of many other ISA extensions and this commit adds correct dependencies to "Zicsr". Additional (2): In RISC-V, "G" is an abbreviation of following extensions: * "I" * "M" * "A" * "F" * "D" * "Zicsr" (although implied by "F") * "Zifencei" and all RISC-V targets with the "G" abbreviation and targets for Android / VxWorks are updated accordingly. Note: Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC. For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates riscv32-wrs-vxworks though).

Amanieu · 2025-04-02T01:16:49Z

@bors r+

bors · 2025-04-02T01:16:52Z

📌 Commit 6f40f0c has been approved by Amanieu

It is now in the queue for this repository.

a4lg · 2025-04-02T01:22:46Z

Reflected the changes (mainly based on the reviews but with an additional implication that is enabled by now merged #138742) and... thanks for approving!

Rollup of 14 pull requests Successful merges: - rust-lang#135295 (Check empty SIMD vector in inline asm) - rust-lang#138003 (Add the new `amx` target features and the `movrs` target feature) - rust-lang#138823 (rustc_target: RISC-V: add base `I`-related important extensions) - rust-lang#138913 (Remove even more instances of `@ts-expect-error` from search.js) - rust-lang#138941 (Do not mix normalized and unnormalized caller bounds when constructing param-env for `receiver_is_dispatchable`) - rust-lang#139060 (replace commit placeholder in vendor status with actual commit) - rust-lang#139102 (coverage: Avoid splitting spans during span extraction/refinement) - rust-lang#139191 (small opaque type/borrowck cleanup) - rust-lang#139200 (Skip suggest impl or dyn when poly trait is not a real trait) - rust-lang#139208 (fix dead link netbsd.md) - rust-lang#139210 (chore: remove redundant backtick) - rust-lang#139212 (Update mdbook to 0.4.48) - rust-lang#139214 (Tell rustfmt to use the 2024 edition in ./x.py fmt) - rust-lang#139225 (move autodiff from EnzymeAD/Enzyme to our rust-lang/Enzyme soft-fork) r? `@ghost` `@rustbot` modify labels: rollup

Rollup merge of rust-lang#138823 - a4lg:riscv-feature-addition-base-i, r=Amanieu rustc_target: RISC-V: add base `I`-related important extensions Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria: * Formerly a part of the `I` extension and splitted thereafter (now ratified as `I` + `Zifencei` + `Zicsr` + `Zicntr` + `Zihpm`) or * Dicoverable from newer versions of the Linux kernel and implemented as a part of `std_detect`'s feature (`Zihintpause`) and * Available on LLVM 18. This is based on [the latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications). LLVM Definitions: * [`Zifencei`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L133-L137) * [`Zicsr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L116-L120) * [`Zicntr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L122-L124) * [`Zihpm`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L153-L155) * [`Zihintpause`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L139-L144) Additional (1): One of those, `Zicsr`, is a dependency of many other ISA extensions and this commit adds correct dependencies to `Zicsr`. Additional (2): In RISC-V, `G` is an abbreviation of following extensions: * `I` * `M` * `A` * `F` * `D` * `Zicsr` (although implied by `F`) * `Zifencei` and all RISC-V targets with the `G` abbreviation and targets for Android / VxWorks are updated accordingly. Note: Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC. For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates `riscv32-wrs-vxworks` though). -------- This is the version 4. `Ztso` in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental `Ztso` requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding `Ztso` is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry `Zihintpause`). Version 4: * Fixed some commit messages, * Added Android / VxWorks targets to imply `G` and * Added an implication from `Zve32x` to `Zicsr` (which makes all vector extension subsets to imply `Zicsr`) since rust-lang#138742 is now merged. Related: * rust-lang#44839 (`riscv_target_feature`) * rust-lang#114544 (This PR can be a prerequisite of resolving a part of that tracking issue) * rust-lang#138742 (Touches the same place and vector extensions depend on `Zicsr`) NOT Related but linked: * rust-lang#132618 (This PR won't be blocked by this issue since none of those extensions do not change the ABI) `@rustbot` r? `@Amanieu` `@rustbot` label +T-compiler +O-riscv +A-target-feature

rust-lang/rust#138823 added five new extensions as compiler target features. This commit reflects that fact and now checks static target features on `std::arch::is_riscv_feature_detected!` as well. * "Zicsr" * "Zicntr" * "Zihpm" * "Zifencei" * "Zihintpause"

…2, r=Amanieu rustc_target: RISC-V: feature addition batch 2 Of ratified RISC-V extensions, this commit adds ones satisfying following criteria: 1. Either discoverable through a `riscv_hwprobe` system call on Linux 6.14 or should be very helpful even on basic needs (the `B` extension), 2. Does not disrupt current Rust's feature handling mechanism and 3. Not too OS-dependent (the `Supm` extension) Due to 2., the author excluded `Zcf` (RV32 only) and `Zcd` from the list despite that they are discoverable from Linux 6.14. Due to 3., the author excluded the `Supm` extension on the PR version 2. This is based on the specification: * [The latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications) Linux Definition: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwprobe.h LLVM Definitions: * [`B`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L507-L510) * [`Zca`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L395-L398) * [`Zcb`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L407-L410) * [`Zcmop`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L460-L463) * [`Zfa`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L335-L338) * [`Zicboz`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L89-L92) * [`Zicond`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L125-L128) * [`Zihintntl`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L148-L151) * [`Zimop`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L161-L162) * [`Ztso`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L214-L217) The author also adds required implication: `C` implies `Zca`. Android RISC-V target is also updated to include the `B` extension (this is just a shorthand combination of `Zba`, `Zbb` and `Zbs` extensions but possibly simplifies `target_feature` handling). # History ## Version 1 → 2 * Remove the `Supm` extension from the Rust target features (thanks, `@Amanieu).` -------- Related: * rust-lang#44839 (`riscv_target_feature`) * rust-lang#138823 (my previous batch) * rust-lang#132618 (stabilization of the `Zfa` extension is blocked by this) `@rustbot` r? `@Amanieu` `@rustbot` label +T-compiler +O-riscv +A-target-feature

Rollup merge of rust-lang#139440 - a4lg:riscv-feature-addition-batch-2, r=Amanieu rustc_target: RISC-V: feature addition batch 2 Of ratified RISC-V extensions, this commit adds ones satisfying following criteria: 1. Either discoverable through a `riscv_hwprobe` system call on Linux 6.14 or should be very helpful even on basic needs (the `B` extension), 2. Does not disrupt current Rust's feature handling mechanism and 3. Not too OS-dependent (the `Supm` extension) Due to 2., the author excluded `Zcf` (RV32 only) and `Zcd` from the list despite that they are discoverable from Linux 6.14. Due to 3., the author excluded the `Supm` extension on the PR version 2. This is based on the specification: * [The latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications) Linux Definition: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwprobe.h LLVM Definitions: * [`B`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L507-L510) * [`Zca`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L395-L398) * [`Zcb`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L407-L410) * [`Zcmop`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L460-L463) * [`Zfa`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L335-L338) * [`Zicboz`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L89-L92) * [`Zicond`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L125-L128) * [`Zihintntl`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L148-L151) * [`Zimop`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L161-L162) * [`Ztso`](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L214-L217) The author also adds required implication: `C` implies `Zca`. Android RISC-V target is also updated to include the `B` extension (this is just a shorthand combination of `Zba`, `Zbb` and `Zbs` extensions but possibly simplifies `target_feature` handling). # History ## Version 1 → 2 * Remove the `Supm` extension from the Rust target features (thanks, `@Amanieu).` -------- Related: * rust-lang#44839 (`riscv_target_feature`) * rust-lang#138823 (my previous batch) * rust-lang#132618 (stabilization of the `Zfa` extension is blocked by this) `@rustbot` r? `@Amanieu` `@rustbot` label +T-compiler +O-riscv +A-target-feature

rustbot assigned Amanieu Mar 22, 2025

a4lg mentioned this pull request Mar 22, 2025

rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742

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a4lg force-pushed the riscv-feature-addition-base-i branch from 1649e52 to e04fb06 Compare March 24, 2025 02:30

a4lg changed the title ~~rustc_target: Sync with stdarch (important parts)~~ rustc_target: RISC-V: add base I-related important extensions Mar 24, 2025

a4lg force-pushed the riscv-feature-addition-base-i branch from e04fb06 to b87155b Compare March 24, 2025 02:41

a4lg force-pushed the riscv-feature-addition-base-i branch from b87155b to 6f40f0c Compare April 2, 2025 01:15

bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Apr 2, 2025

Zalathar mentioned this pull request Apr 2, 2025

Rollup of 14 pull requests #139229

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bors merged commit 6aec7de into rust-lang:master Apr 2, 2025
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rustbot added this to the 1.88.0 milestone Apr 2, 2025

a4lg mentioned this pull request Apr 6, 2025

rustc_target: RISC-V: feature addition batch 2 #139440

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a4lg mentioned this pull request Apr 6, 2025

RISC-V: check cfg (batch 1) rust-lang/stdarch#1764

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a4lg mentioned this pull request Apr 30, 2025

rustc_target: RISC-V: feature addition batch 3 #140507

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