As part of the Digital VLSI laboratory exercise at ECE NTUA, Ioannis Danias and I designed a FIR filter for the Zybo board using VHDL. The filter communicates with the board via AXI4-LITE and was designed in Xilinx Vivado. We kept the de# a single file because it was easier for Vivado to handle it that way.
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stavrakas13/FIR-filter-for-FPGA-Zybo
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As part of the laboratory exercise of Dig. VSLI in ECE NTUA, me and Ioannis Danias, we designed in VHDL, a FIR filter for the Zybo board which communicates with it via AXI LITE.
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