Fix alignment exceptions issue for F and C extensions #317
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Current F extnesion implementation did not properly handle address alignment concerns. A check for address misalignment has been introduced, and the corresponding exception handler is invoked to ensure correct behavior. Reported-by: Shi-Sheng Yang <james1qaz2wsx12qw@gmail.com>
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jserv
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qwe661234
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| @@ -346,13 +350,7 @@ static block_t *block_find(const block_map_t *map, const uint32_t addr) | |||
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| FORCE_INLINE bool insn_is_misaligned(uint32_t pc) | |||
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I wonder if insn_is_misaligned is really used via macro expansion or not. Can you check?
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I inserted a fprintf statement inside insn_is_misaligned() to verify if the function is being executed. It should not run during make ENABLE_EXT_C=1 check but should run during make ENABLE_EXT_C=0 check. My experimental results align with my expectations.
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Then, insn_is_misaligned should be conditionally built, depending on the configurations.
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I tried executing the command @qwe661234, can you help confirm? |
According to the riscv-spec-v2.2 Chapter 12 page 67 [1], under the C extension, jump-related instructions should not trigger any misaligned instruction address exceptions. However, the current implementation checks whether the instruction address is aligned to 16-bit, which is incorrect and could potentially cause a performance hit. This patch eliminates unnecessary misalignment checks for jump instructions when the C extension is enabled, aligning the behavior with the expected specification. Link: https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf [1]
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The current master branch also encounters the same error. |
Let's create an issue which describes the above build failure. |
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Thank @visitorckw for contributing! |
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Fix alignment exceptions issue for F and C extensions
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This pull request address two issues related to data/instruction address alignment exceptions. The first patch adds address alignment checks for F extension load/store operations, resolving an issue reported by @fourcolor. The second patch fixes incorrect alignment checks in the C extension, aligning behavior with RISC-V specifications by eliminating unnecessary misalignment checks for jump instructions.